External Memory Interfaces Intel® Cyclone® 10 GX FPGA IP User Guide

ID 683663
Date 3/29/2021
Document Table of Contents

6.4. DDR3 Board Design Guidelines

The following topics provide guidelines for improving the signal integrity of your system and for successfully implementing a DDR3 SDRAM interface on your system.

The following areas are discussed:

  • I/O standards
  • comparison of various types of termination schemes, and their effects on the signal quality on the receiver
  • proper drive strength setting on the FPGA to optimize the signal integrity at the receiver
  • effects of different loading types, such as components versus DIMM configuration, on signal quality

I/O Standards

DDR3 SDRAM interface signals use one of the following JEDEC* I/O signaling standards:

  • SSTL-15—for DDR3.
  • SSTL-135—for DDR3L.

Termination Schemes

It is important to understand the trade-offs between different types of termination schemes, the effects of output drive strengths, and different loading types, so that you can swiftly navigate through the multiple combinations and choose the best possible settings for your designs.

The following key factors affect signal quality at the receiver:

  • Leveling and dynamic ODT
  • Proper use of termination
  • Layout guidelines

As memory interface performance increases, board designers must pay closer attention to the quality of the signal seen at the receiver because poorly transmitted signals can dramatically reduce the overall data-valid margin at the receiver. The following figure shows the differences between an ideal and real signal seen by the receiver.

Figure 42. Ideal and Real Signal at the Receiver

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