External Memory Interfaces Intel® Cyclone® 10 GX FPGA IP User Guide

ID 683663
Date 3/29/2021

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3.1.3. I/O AUX

Each column includes one I/O AUX, which contains a hardened Nios II processor with dedicated memory. The I/O AUX is responsible for calibration of all the external memory interfaces in the column.

The I/O AUX includes dedicated memory which stores both the calibration algorithm and calibration run-time data. The hardened Nios II processor and the dedicated memory can be used only by an external memory interface, and cannot be employed for any other use. The I/O AUX can interface with soft logic, such as the debug toolkit, via an Avalon® -MM bus.

The I/O AUX is clocked by an on-die oscillator, and therefore does not consume a PLL.