External Memory Interfaces Intel® Cyclone® 10 GX FPGA IP User Guide

ID 683663
Date 3/29/2021
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

4.1.1.11. afi_clk for DDR3

AFI clock interface

Table 19.  Interface: afi_clkInterface type: Clock Output
Port Name Direction Description
afi_clk Output Clock for the Altera PHY Interface (AFI)