External Memory Interfaces Intel® Cyclone® 10 GX FPGA IP User Guide
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7.1.6. Intel Cyclone 10 GX EMIF IP LPDDR3 Parameters: Board
Display Name | Description |
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Use default ISI/crosstalk values | You can enable this option to use default intersymbol interference and crosstalk values for your topology. Note that the default values are not optimized for your board. For optimal signal integrity, it is recommended that you do not enable this parameter, but instead perform I/O simulation using IBIS models and Hyperlynx)*, and manually enter values based on your simulation results, instead of using the default values. (Identifier: BOARD_LPDDR3_USE_DEFAULT_ISI_VALUES) |
Address and command ISI/crosstalk | The address and command window reduction due to intersymbol interference and crosstalk effects. The number to be entered is the total loss of margin on the setup and hold sides (measured loss on the setup side + measured loss on the hold side). Refer to the EMIF Simulation Guidance wiki page for additional information. (Identifier: BOARD_LPDDR3_USER_AC_ISI_NS) |
Read DQS/DQS# ISI/crosstalk | The reduction of the read data window due to ISI and crosstalk effects on the DQS/DQS# signal when driven by the memory device during a read. The number to be entered is the total loss of margin on the setup and hold sides (measured loss on the setup side + measured loss on the hold side). Refer to the EMIF Simulation Guidance wiki page for additional information. (Identifier: BOARD_LPDDR3_USER_RCLK_ISI_NS) |
Read DQ ISI/crosstalk | The reduction of the read data window due to intersymbol inteference and crosstalk effects on the DQ signal when driven by the memory device during a read. The number to be entered is the total loss of margin on the setup and hold sides (measured loss on the setup side + measured loss on the hold side). Refer to the EMIF Simulation Guidance wiki page for additional information. (Identifier: BOARD_LPDDR3_USER_RDATA_ISI_NS) |
Write DQS/DQS# ISI/crosstalk | The reduction of the write data window due to intersymbol interference and crosstalk effects on the DQS/DQS# signal when driven by the FPGA during a write. The number to be entered is the total loss of margin on the setup and hold sides (measured loss on the setup side + measured loss on the hold side). Refer to the EMIF Simulation Guidance wiki page for additional information. (Identifier: BOARD_LPDDR3_USER_WCLK_ISI_NS) |
Write DQ ISI/crosstalk | The reduction of the write data window due to intersymbol interference and crosstalk effects on the DQ signal when driven by the FPGA during a write. The number to be entered is the total loss of margin on the setup and hold sides (measured loss on the setup side + measured loss on the hold side). Refer to the EMIF Simulation Guidance wiki page for additional information. (Identifier: BOARD_LPDDR3_USER_WDATA_ISI_NS) |
Display Name | Description |
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Package deskewed with board layout (DQS group) | Enable this parameter if you are compensating for package skew on the DQ, DQS, and DM buses in the board layout. Include package skew in calculating the following board skew parameters. (Identifier: BOARD_LPDDR3_IS_SKEW_WITHIN_DQS_DESKEWED) |
Maximum board skew within DQS group | The largest skew between all DQ and DM pins in a DQS group. This value affects the read capture and write margins. (Identifier: BOARD_LPDDR3_BRD_SKEW_WITHIN_DQS_NS) |
Maximum system skew within DQS group | The largest skew between all DQ and DM pins in a DQS group. Enter combined board and package skew. This value affects the read capture and write margins. (Identifier: BOARD_LPDDR3_PKG_BRD_SKEW_WITHIN_DQS_NS) |
Package deskewed with board layout (address/command bus) | Enable this parameter if you are compensating for package skew on the address, command, control, and memory clock buses in the board layout. Include package skew in calculating the following board skew parameters. (Identifier: BOARD_LPDDR3_IS_SKEW_WITHIN_AC_DESKEWED) |
Maximum board skew within address/command bus | The largest skew between the address and command signals. Enter the board skew only; package skew is calculated automatically, based on the memory interface configuration, and added to this value. (Identifier: BOARD_LPDDR3_BRD_SKEW_WITHIN_AC_NS) |
Maximum system skew within address/command bus | Maximum system skew within address/command bus refers to the largest skew between the address and command signals. (Identifier: BOARD_LPDDR3_PKG_BRD_SKEW_WITHIN_AC_NS) |
Average delay difference between DQS and CK | The average delay difference between the DQS signals and the CK signal, calculated by averaging the longest and smallest DQS trace delay minus the CK trace delay. Positive values represent DQS signals that are longer than CK signals and negative values represent DQS signals that are shorter than CK signals. (Identifier: BOARD_LPDDR3_DQS_TO_CK_SKEW_NS) |
Maximum delay difference between devices | This parameter describes the largest propagation delay on the DQ signals between ranks. For example, in a two-rank configuration where devices are placed in series, there is an extra propagation delay for DQ signals going to and coming back from the furthest device compared to the nearest device. This parameter is only applicable when there is more than one rank. (Identifier: BOARD_LPDDR3_SKEW_BETWEEN_DIMMS_NS) |
Maximum skew between DQS groups | The largest skew between DQS signals. (Identifier: BOARD_LPDDR3_SKEW_BETWEEN_DQS_NS) |
Average delay difference between address/command and CK | The average delay difference between the address/command signals and the CK signal, calculated by averaging the longest and smallest address/command signal trace delay minus the maximum CK trace delay. Positive values represent address and command signals that are longer than CK signals and negative values represent address and command signals that are shorter than CK signals. (Identifier: BOARD_LPDDR3_AC_TO_CK_SKEW_NS) |
Maximum CK delay to device | The maximum CK delay to device refers to the delay of the longest CK trace from the FPGA to any device. (Identifier: BOARD_LPDDR3_MAX_CK_DELAY_NS) |
Maximum DQS delay to device | The maximum DQS delay to device refers to the delay of the longest DQS trace from the FPGA to any device (Identifier: BOARD_LPDDR3_MAX_DQS_DELAY_NS) |