External Memory Interfaces Intel® Cyclone® 10 GX FPGA IP User Guide

ID 683663
Date 3/29/2021
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4.1.2.16. cal_debug_reset_n for LPDDR3

User calibration debug clock domain reset interface

Table 57.  Interface: cal_debug_reset_nInterface type: Reset Input
Port Name Direction Description
cal_debug_reset_n Input Reset for the user clock connecting to the Avalon calibration debug bus. Asynchronous assertion and synchronous deassertion