5.2.5. Functional Simulation with VHDL
Prior to Intel® Quartus® Prime version 15.1, the VHDL fileset was comprised entirely of VHDL files. Beginning with Intel® Quartus® Prime version 15.1, only the top-level IP instance file is guaranteed to be written in VHDL; submodules can still be deployed as Verilog/SystemVerilog (encrypted or plain text) files, or VHDL files. Note that the Questa - Intel FPGA Edition is no longer restricted to a single HDL language as of Intel® Quartus® Prime 15.1; however, some files may still be encrypted in order to be excluded from the maximum unencrypted module limit of this tool.
Because the VHDL fileset consists of both VHDL and Verilog files, you must follow certain mixed-language simulation guidelines. The general guideline for mixed-language simulation is that you must always link the Verilog files (whether encrypted or not) against the Verilog version of the libraries, and the VHDL files (whether SimGen-generated or pure VHDL) against the VHDL libraries.
Simulation scripts for the Synopsys* , Cadence, Aldec, and Siemens EDA simulators are provided for you to run the example design. These simulation scripts are located in the following main folder locations:
Simulation scripts in the simulation folders are located as follows:
For more information about simulating Verilog HDL or VHDL designs using command lines, refer to the Intel® Quartus® Prime Pro Edition User Guide, Third-party Simulation.
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