Video and Image Processing Suite User Guide

ID 683416
Date 2/12/2021

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

19.2. Interlacer Control Registers

Table 61.  Interlacer II Register MapYou may choose to enable an Avalon-MM control slave interface for the Interlacer II IP core to enable run-time updating of the coefficient values. As is the convention with all VIP IP cores, when a control slave interface is included, the IP core resets into a stopped state and must be started by writing a ‘1’ to the Go bit of the control register before any input data is processed.
Address Register Description
0 Control Bit 0 of this register is the Go bit. All other bits are unused. Setting this bit to 0 causes the IP core to stop at the end of the next frame/field packet.

When you enable run-time control, the Go bit gets deasserted by default. If you do not enable run-time control, the Go is asserted by default.

1 Status Bit 0 of this register is the Status bit, all other bits are unused. The IP core sets this address to 0 between frames. The IP core sets this address to 1 when it is processing data and cannot be stopped.
2 Interrupt This bit is not used because the IP core does not generate any interrupts.
3 Settings
  • Bit 0 enables and disables progressive passthrough.
  • Bit 1 enables and disables interlaced passthrough.
  • Bit 2 enables and disables control packet interlaced nibble override.
  • Bit 3 indicates whether the output interlaced sequence should begin with F0 or F1. Set to 0 for F0 and 1 for F1.
  • Bit 4 allows you to reset the interlacing sequence at run time. To reset the interlaced sequence first stop the IP core using the Go bit in register 0, then write a 1 to bit 4 of this register, and then restart the IP core.
All other bits are unused.