Video and Image Processing Suite User Guide

ID 683416
Date 2/12/2021
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Give Feedback

15.9.1. Approach A

Approach A is for motion adaptive with 3:2 and 2:2 detector with video over film configurations where 4K HDR and SDR passthrough is natively supported but require fMAX conversion.
Figure 62. 4K Video Passthrough (10-bit 4:4:4 YCbCr)The figure below shows the recommended approach to convert the data coming in and out of the deinterlacer.
The following sequences describe the conversion:
  1. The Color Plane Sequencer II IP core converts between 2 and 4 pixels in parallel.
  2. Dual-clock FIFOs (Avalon-ST Dual Clock FIFO IP core) transfer data with a 50% duty cycle on the Avalon-ST valid signal in a 300MHz clock domain to 100% duty cycle in a 150MHz clock domain.
  3. The deinterlacer accepts pixels in parallel data and converts any interlaced content to 1 pixel in parallel for deinterlacing.
  4. Progressive content (and user packets) is maintained at the configured number of pixels in parallel and is unaffected by passing through the deinterlacer.