Video and Image Processing Suite User Guide

ID 683416
Date 2/12/2021

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Document Table of Contents

A. Avalon-ST Video Verification IP Suite

The Avalon-ST Video Verification IP Suite provides a set of SystemVerilog classes (the class library) that you can use to ensure that a video IP simulates correctly and conforms to the Avalon-ST video standard.
Figure 83. Test Environment for the Avalon-ST Video Class LibraryThe figure below shows the elements in the Avalon-ST Video Verification IP Suite. Yellow indicates the class library components of the test environment, green indicates the Avalon-ST Bus Functional Model (BFM) as instanced in the Platform Designer environment, purple indicates the test method calls themselves, and blue indicates the device under test (DUT).

The DUT is fed with Avalon-ST Video-compliant video packets and control packets. The packets are either constrained randomly or derived from a test video file. The responses from the DUT are collected, analyzed, and any resultant video written to an output file.

The class library uses the Avalon-MM and Avalon-ST source and sink BFMs [1] and provides the following functionality:
  • Embodies the pixels-in-parallel upgrades to the Avalon-ST Video standard to facilitate compliance testing.
  • Implements a host of common Avalon-ST Video protocol failures that the DUT can be tested against. You can configure these using simple method calls to the class library.
  • Implements file reader or file writer functionality to facilitate DUT testing with real video sequences.
  • Uses SystemVerilog’s powerful verification features such as mailboxes and randomization of objects. These features allow you to easily construct complex and noisy bus environments for rigorous stress-testing of DUTs.