Visible to Intel only — GUID: bhc1411020386571
Ixiasoft
Visible to Intel only — GUID: bhc1411020386571
Ixiasoft
20.6. Scaler II Control Registers
The control data is read once at the start of each frame and is buffered inside the IP core, so the registers can be safely updated during the processing of a frame.
Address | Register | Description |
---|---|---|
0 | Control |
|
1 | Status | Bit 0 of this register is the Status bit, all other bits are unused.
|
2 | Interrupt | This bit is not used because the IP core does not generate any interrupts. |
3 | Output Width | The width of the output frames in pixels. |
4 | Output Height | The height of the output frames in pixels. |
5 | Edge Threshold | Specifies the minimum difference between neighboring pixels beyond which the edge-adaptive algorithm switches to using the edge coefficient set. To get the threshold used internally, this value is multiplied by the number of color planes per pixel. |
6 | – | Reserved. |
7 | – | Reserved. |
8 | Horizontal Coefficient Write Bank | Specifies which memory bank horizontal coefficient writes from the Avalon-MM interface are made into. |
9 | Horizontal Coefficient Read Bank | Specifies which memory bank is used for horizontal coefficient reads during data processing. |
10 | Vertical Coefficient Write Bank | Specifies which memory bank vertical coefficient writes from the Avalon-MM interface are made into. |
11 | Vertical Coefficient Read Bank | Specifies which memory bank is used for vertical coefficient reads during data processing. |
12 | Horizontal Phase | Specifies which horizontal phase the coefficient tap data in the Coefficient Data register applies to. Writing to this location, commits the writing of coefficient tap data. This write must be made even if the phase value does not change between successive sets of coefficient tap data. To commit to an edge phase, write the horizontal phase number +32768. For example, set bit 15 of the register to 1. |
13 | Vertical Phase | Specifies which vertical phase the coefficient tap data in the Coefficient Data register applies to. Writing to this location, commits the writing of coefficient tap data. This write must be made even if the phase value does not change between successive sets of coefficient tap data. To commit to an edge phase, write the vertical phase number +32768. For example, set bit 15 of the register to 1. |
14 to 14+Ntaps | Coefficient Data | Specifies values for the coefficients at each tap of a particular horizontal or vertical phase. Write these values first, then the Horizontal Phase or Vertical Phase, to commit the write. |