Video and Image Processing Suite User Guide

ID 683416
Date 2/12/2021

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

14.1. Using the Control Synchronizer IP Core

The example illustrates how the Control Synchronizer IP Core is set to trigger on the changing of the width field of control data packets.

In the following example, the Control Synchronizer IP Core is placed in a system containing the following IP cores:

  • Test Pattern Generator II
  • Frame Buffer II
  • Scaler II

The Control Synchronizer IP core must synchronize a change of the width of the generated video packets with a change to the scaler output size in the following conditions:

  • The scaler maintains a scaling ratio of 1:1 (no scaling)
  • The frame buffer is configured to drop and repeat making it impossible to calculate packets streamed into the frame buffer and streamed out to the scaler.
  • The scaler cannot be configured in advance of a certain video data packet.

The Control Synchronizer IP Core solves the problem through the following sequence of events:

  1. Sets up the change of video width.
    Figure 50. Change of Video Width
  2. The test pattern generator changes the size of its Video Data Packet and Control Data Packet pairs to 320 width. It is not known when this change will propagate through the frame buffer to the scaler.
    Figure 51. Changing Video Width
  3. The Video Data Packet and Control Data Packet pair with changed width of 320 propagates through the frame buffer. The control synchronizer detects the change and triggers a write to the scaler. The control synchronizer stalls the video processing pipeline while it performs the write.
    Figure 52. Test Pattern Generator Change
  4. The scaler is reconfigured to output width 320 frames. The control synchronizer resumes the video processing pipeline. The scaling ratio maintains at 1:1.
    Figure 53. Reconfigured Scaler II