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20.3. Polyphase and Bicubic Algorithm
The polyphase and bicubic algorithms allow scaling to be performed in such a way as to preserve sharp edges, but without losing the smooth interpolation effect on graduated areas. For down scaling, a long polyphase filter can reduce aliasing effects.
The bicubic and polyphase algorithms use different mathematics to derive their filter coefficients. The implementation of the bicubic algorithm is just the polyphase algorithm with four vertical and four horizontal taps. In the following discussion, all comments relating to the polyphase algorithm are applicable to the bicubic algorithm assuming 4×4 taps.
Consider the following for an instance of the polyphase scaler.
- Nv = vertical taps
- Nh = horizontal taps
- Bdata = bit width of the data samples
- Bv = bit width of the vertical coefficients
- Bh = bit width of the horizontal coefficients
- Pv = user-defined number of vertical phases for each coefficient set (must be a power of 2)
- Ph = user-defined number of horizontal phases for each coefficient set (must be a power of 2)
- Cv = number of vertical coefficient banks
- Ch = number of horizontal coefficient banks
The total number of multipliers is Nv + Nh per channel in parallel.
The width of each vertical multiplier is max(Bdata, Bv )
The width of each horizontal multiplier is the maximum of the horizontal coefficient width, Bh, and the bit width of the horizontal kernel, Bkh .
The bit width of the horizontal kernel determines the precision of the results of vertical filtering and is user-configurable.
The memory requirement is Nv line-buffers plus vertical and horizontal coefficient banks. As in the nearest-neighbor and bilinear methods, each line buffer is the same size as one line from the clipped input image.
The vertical coefficient banks are stored in memory that is Bv bits wide and Pv ×Nv ×Cv words deep. The horizontal coefficient banks are stored in memory that is Bh ×Nh bits wide and Ph ×Ch words deep. For each coefficient type, the Intel® Quartus® Prime software maps these appropriately to physical on-chip RAM or logic elements as constrained by the width and depth requirements.
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