Video and Image Processing Suite User Guide

ID 683416
Date 2/12/2021
Public

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16.5. Frame Buffer Parameter Settings

Table 53.  Frame Buffer II Parameter Settings
Parameter Value Description
Maximum frame width 32–8192, Default = 1920 Specify the maximum frame width in pixels.
Maximum frame height 32–8192, Default = 1080 Specify the maximum progressive frame height in pixels.
Bits per color sample 4–20, Default = 20 Select the number of bits per pixel (per color plane).
Number of color planes 1–4, Default = 2 Select the number of color planes that are sent in sequence.
Color planes transmitted in parallel On or Off
  • Turn on to transmit color planes in parallel.
  • Turn off to transmit color planes in series.
Number of pixels in parallel 1, 2, 4, or 8 Specify the number of pixels transmitted or received in parallel.
Interlace support On or Off Turn on to support consistent dropping and repeating of fields in an interlaced video stream.
Note: Do not turn on this parameter to double-buffer an interlaced input stream on a field-by-field basis.
Use separate clock for the Avalon-MM master interface(s) On or Off Turn on to add a separate clock signal for the Avalon-MM master interfaces so that they can run at a different speed to the Avalon-ST processing. This decouples the memory speed from the speed of the data path, and is sometimes necessary to reach performance target.
Avalon-MM master(s) local ports width 16-512, Default = 256 Specify the width of the Avalon-MM ports used to access external memory.
FIFO depth Write 16–1024, Default = 64 Select the FIFO depth of the write-only Avalon-MM interface.
Av-MM burst target Write 2–256, Default = 32 Select the burst target for the write-only Avalon-MM interface.
FIFO depth Read 16–1024, Default = 64 Select the FIFO depth of the read-only Avalon-MM interface.
Av-MM burst target Read 2–256, Default = 32 Select the burst target for the read-only Avalon-MM interface.
Align read/write bursts on read boundaries On or Off Turn on to avoid initiating read and write bursts at a position that would cause the crossing of a memory row boundary.
Maximum ancillary packets per frame Any 32-bit value, Default = 0 Specify the number of non-image, non-control, Avalon-ST Video packets that can be buffered with each frame. Older packets are discarded first in case of an overflow.
Note: The Maximum length ancillary packets in symbols parameter is disabled or unused when you specify the number of packets buffered per frame to 0.
User packets are no longer delayed through the DDR memory (as with the Frame Buffer I IP core). The packets are instead grouped at the output immediately following the next control packet. Then the video packets swap places with the user packets which arrive before the next control packet.
Maximum length ancillary packets in symbols 10–1024,Default = 10 Select the maximum packet length as a number of symbols. The minimum value is 10 because this is the size of an Avalon-ST control packet (header included). Extra samples are discarded if the packets are larger than allowed.
Frame buffer memory base address Any 32-bit value, Default = 0x00000000 Select a hexadecimal address of the frame buffers in external memory when buffering is used. The information message displays the number of frame buffers and the total memory required at the specified base address.
Enable use of inter-buffer offset On or Off Turn on if you require maximum DDR efficiency, at the cost of increased memory footprint per frame.
Inter-buffer offset Any 32-bit value, Default = 0x01000000 Specify a value greater than the size of an individual frame buffer.
Module is Frame Reader only On or Off Turn on if you want to configure the frame buffer to be a frame reader..
Note: You must select run-time reader control if you select frame reader only.
Module is Frame Writer only On or Off Turn on if you want to configure the frame buffer to be a frame writer.
Note: You must select run-time writer control if you select frame writer only.
Frame dropping On or Off Turn on to allow frame dropping.
Frame repeating On or Off Turn on to allow frame repetition.
Delay length (frames) 1–2047, Default = 1 When you turn on the Drop/repeat user packets parameters, the IP core implements a minimum of 3 buffers (triple buffer), which gives a delay through the buffer of 1 frame.

You can configure the IP core the implement more frame buffers and create a longer delay, up to a maximum of 2047 frames.

This feature enables the pausing of a video stream up to 2048 seconds (input frames per second), by applying the back-pressure to the Avalon-ST video output of the frame buffer for the duration of the pause.

Locked rate support On or Off Turn on to add an Avalon-MM slave interface that synchronizes the input and output frame rates.
Note: You can only turn on this parameter if you also turn on Frame dropping, Frame repeating, and Run-time writer control parameters.
Drop invalid frames On or Off Turn on to drop image data packets that have lengths that are not compatible with the dimensions declared in the last control packet.
Drop/repeat user packets On or Off Turn on to drop or repeat user packets when associated frames are dropped or repeated.
Run-time writer control On or Off Run-time control for the write interface.

The Frame Buffer II has two sides – a reader and a writer. Each side has a register interface, one of which can be configured to be visible to the user. Both control interfaces contain all the necessary registers to control the behavior of the IP core while for the writer, registers 3 and 4 (frame counter and drop/repeat counter) reflect information on dropped frames.

Note: When you turn on this parameter, the Go bit gets deasserted by default. When you turn off this parameter, the Go is asserted by default.

Refer to the Frame Buffer II Control Register Map.

Run-time reader control On or Off Run-time control for the read interface.

The Frame Buffer II has two sides – a reader and a writer. Each side has a register interface, one of which can be configured to be visible to the user. Both control interfaces contain all the necessary registers to control the behavior of the IP core while for the reader, registers 3 and 4 (frame counter and drop/repeat counter) reflect information on repeated frames.

Note: When you turn on this parameter, the Go bit gets deasserted by default. When you turn off this parameter, the Go is asserted by default.

Refer to the Frame Buffer II Control Register Map.