Video and Image Processing Suite User Guide

ID 683416
Date 2/12/2021
Public

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7.11.3. Clocked Video Input II Control Registers

Table 25.  Clocked Video Input II Registers
Address Register Description
0 Control
  • Bit 0 of this register is the Go bit. Setting this bit to 1 causes the CVI II IP core to start data output on the next video frame boundary.
  • Bits 3, 2, and 1 of the Control register are the interrupt enables:
    • Setting bit 1 to 1, enables the status update interrupt.
    • Setting bit 2 to 1, enables the end of field/frame video interrupt.
1 Status
  • Bit 0 of this register is the Status bit. This bit is asserted when the CVI IP core is producing data.
  • Bits 6–1 of the Status register are unused.
  • Bit 7 is the interlaced bit. When asserted, the input video stream is interlaced.
  • Bit 8 is the stable bit. When asserted, the input video stream has had a consistent line length for two of the last three lines.
  • Bit 9 is the overflow sticky bit. When asserted, the input FIFO has overflowed. The overflow sticky bit stays asserted until a 1 is written to this bit.
  • Bit 10 is the resolution bit. When asserted, indicates a valid resolution in the sample and line count registers.
  • Bit 11 is the vid_locked bit. When asserted, indicates current signal value of the vid_locked signal.
  • Bit 12 is the clipping bit. When asserted, input video frame/field is being clipped to match the resolution specified in the control packet.
    Note: Present only when you turn on Enable matching data packet to control by clipping.
  • Bit 13 is the padding bit. When asserted, input video frame/field is being padded to match the resolution specified in the control packet.
    Note: Present only when you turn on Enable matching data packet to control by padding.
  • Bit 14 is the picture drop sticky bit. When asserted, indicates one or more picture(s) has been dropped at input side. It stays asserted until a 1 is written to this bit.
  • Bits 21–15 give the picture drop count. When picture drop sticky bit is asserted, this drop count provides the number of frame/field dropped at the input. Count resets when you clear the picture drop sticky bit.
    Note: Both picture drop sticky and picture drop count bit are present only when you turn on Enable matching data packet to control by padding and/or Overflow handling.
2 Interrupt Bits 2 and 1 are the interrupt status bits:
  • When bit 1 is asserted, the status update interrupt has triggered.
  • When bit 2 is asserted, the end of field/frame interrupt has triggered.
  • The interrupts stay asserted until a 1 is written to these bits.
3 Used Words The used words level of the input FIFO.
4 Active Sample Count The detected sample count of the video streams excluding blanking.
5 F0 Active Line Count The detected line count of the video streams F0 field excluding blanking.
6 F1 Active Line Count The detected line count of the video streams F1 field excluding blanking.
7 Total Sample Count The detected sample count of the video streams including blanking.
8 F0 Total Line Count The detected line count of the video streams F0 field including blanking.
9 F1 Total Line Count The detected line count of the video streams F1 field including blanking.
10 Standard The contents of the vid_std signal.
11-13 Reserved Reserved for future use.
14 Color Pattern
  • Bits 7–0 are for color encoding—captures the value driven on the vid_color_encoding input.
  • Bits 15–8 are for bit width—captures the value driven on the vid_bit_width input.
15 Ancillary Packet Start of the ancillary packets that have been extracted from the incoming video.
15 + Depth of ancillary memory End of the ancillary packets that have been extracted from the incoming video.