Video and Image Processing Suite User Guide

ID 683416
Date 2/12/2021

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26. Avalon-ST Video Monitor IP Core

The Avalon-ST Video Monitor IP core is a debugging and monitoring component.

The Avalon-ST Video Monitor IP core together with the associated software in System Console captures and visualizes the flow of video data in a system. You can inspect the video data flow at multiple levels of abstraction from the Avalon-ST video protocol level down to raw packet data level.

The Avalon-ST Video Monitor IP core enables the visibility of the Avalon-ST video control and data packets streaming between video IP components. To monitor the video control and data packets, you must insert the monitor components into a system.
Figure 82.  Avalon-ST Video Monitor Functional Block DiagramThis figure shows the monitor components in a system.

The monitored Avalon-ST video stream enters the monitor through the din Avalon-ST sink port and leaves the monitor through the dout Avalon-ST source port. The monitor does not modify, delay, or stall the video stream in any way. Inside the monitor, the stream is tapped for you to gather statistics and sample data. The statistics and sampled data are then transmitted through the capture Avalon-ST source port to the trace system component. The trace system component then transmits the received information to the host. You may connect multiple monitors to the Trace System IP core.

Note: System Console uses the sopcinfo file (written by Platform Designer) or the .sof (written by the Intel® Quartus® Prime software) to discover the connections between the trace system and the monitors. If you instantiate and manually connect the trace system and the monitors using HDL, System Console will not detect them.