|IP Core||Internal Interrupts||Description|
|Clocked Video Input II IP||Status update interrupt||Triggers when the stable bit, the resolution valid bit, the overflow sticky bit, or the picture drop sticky bit of the Status register changes value.|
|End of field/frame interrupt||
You can use this interrupt to trigger the reading of the ancillary packets from the control interface before the packets are overwritten by the next frame.
You can independently enable these interrupts using bits [2:1] of the Control register. You can read the interrupt values using bits [2:1] of the Interrupt register. Writing 1 to either of these bits clears the respective interrupt.
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