3.1.3. Separate Synchronization Format
The CVO IP cores create horizontal and vertical syncs and field information through their own signals. The CVO IP cores create a sample for each clock cycle on the vid_data bus. The vid_datavalid signal indicates when the vid_data video output is in an active picture period of the frame.
|vid_h_sync||When 1, the video is in a horizontal synchronization period.|
|vid_v_sync||When 1, the video is in a vertical synchronization period.|
|vid_f||When 1, the video is interlaced and in field 1. When 0, the video is either progressive or interlaced and in field 0.|
|vid_h||When 1, the video is in a horizontal blanking period, (only for Clocked Video Output IP core).|
|vid_v||When 1, the video is in a vertical blanking period, (only for Clocked Video Output IP core).|
|vid_de||When asserted, the video is in an active picture period (not horizontal or vertical blanking). This signal must be driven for correct operation of the IP cores.
Note: Only for Clocked Video Input IP cores.
The CVI IP cores only read the vid_data, vid_de, vid_h_sync, vid_v_sync, and vid_f signals when vid_datavalid is 1. This allows the CVI IP cores to support oversampling where the video clock is running at a higher rate than the pixel clock.
Did you find the information on this page useful?