Video and Image Processing Suite User Guide

ID 683416
Date 2/12/2021
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

22.3. Generation of Avalon-ST Video Control Packets and Run-Time Control

The Test Pattern Generator II IP core produces a valid Avalon-ST Video control packet before generating each image data packet , whether it is a progressive frame or an interlaced field.

When the output is interlaced, the Test Pattern Generator II IP cores produces a sequence of pairs of field, starting with:

  • F0 if the output is F1 synchronized.
  • F1 if the output is F0 synchronized.

When you enable the Avalon slave run-time controller, the resolution of the output can be changed at run-time at a frame boundary, that is, before the first field of a pair when the output is interlaced.

The Test Pattern Generator II IP core does not accept an input stream—so the Avalon-MM slave interface pseudo-code is slightly modified:
go = 0;
while (true)
{
		status = 0;
		while (go != 1 )
				wait();
		read_control(); //Copies control to internal register
		status = 1;
do once for progressive output or twice for interlaced output
{
		send_control_packet();
		send_image_data_header();
		output_test_pattern ();
}
}

Did you find the information on this page useful?

Characters remaining:

Feedback Message