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7.8. Timing Constraints
For these IPs, the .sdc files are automatically included by their respective .qip files. After adding the Platform Designer system to your design in the Intel® Quartus® Prime software, verify that the alt_vip_cvi_core.sdc or alt_vip_cvo_core.sdc has been included.
When you apply the .sdc file, you may see some warning messages similar to the format below:
- Warning: At least one of the filters had some problems and could not be matched.
- Warning: * could not be matched with a keeper.
You should expect these warnings, because in certain configurations the Intel® Quartus® Prime software optimizes unused registers and they no longer remain in your design.
Intel recommends that you place a frame buffer in any CVI to CVO system. Because the CVO II IP generates sync signals for a complete frame, even when video frames end early, the CVO II IP can continually generate backpressure to the CVI II IP so that it keeps ending packets early.
Placing a frame buffer may not be appropriate if the system requires latency lower than 1 frame. In this case, enable the Low Latency mode when you configure the CVO II IP.
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