Triple-Speed Ethernet Intel® FPGA IP User Guide

ID 683402
Date 10/12/2023
Document Table of Contents

9.5. Test Flow

The testbench performs the following operations upon a simulated power-on reset:
  • Initializes the DUT registers.
  • Starts transmission. For a single-channel MAC with internal FIFO buffers, clears the FIFOs.
  • Ends transmission and checks the following elements to determine that the simulation is successful:
    • No Ethernet protocol errors detected.
    • Ethernet frames generated and transmitted are received by the frame monitor.