| November 2017 |
2017.11.06 |
- Rebranded as Intel.
- Renamed the document as Intel FPGA Triple-Speed Ethernet IP Core User Guide.
- Added support for the Intel Stratix 10, Intel Cyclone 10 GX, and and Intel Cyclone 10 LP device families.
- Updated the description of the About This IP Core topic.
- Added "Intel FPGA IP Core Device Support Levels" table to the Device Family Support topic.
- Removed the Definition: Device Support Level topic.
- Updated the "Intel Arria 10 Resource Utilization", "Cyclone V Resource Utilization" table: Updated the IP core name from 1000BASE-X/SGMII PCS with PMA to 1000BASE-X/SGMII PCS.
- Updated the Generating a Design Example or Simulation Model topic:
- Added a note to clarify that the Generate Example Design option only generates the design for functional simulation.
- Added a note to clarify that the dynamically generated design example for functional simulation is available only in Intel Arria 10, Intel Cyclone GX, and Intel Stratix 10 devices.
- Updated the "Recommended Quartus Pin Assignments" table: Updated the Design Pin information for GLOBAL_SIGNAL pin assignment.
- Updated the "Core Configuration Parameters" table:
- Added a note to the description of Interface parameter to clarify that RGMII interface is not supported in Intel Arria 10, Intel Cyclone 10 GX, and Intel Stratix 10 devices from Intel Quartus Prime software version 17.1 onwards.
- Added a note to the description of Number of ports to clarify that the number of ports supported for Triple-Speed Ethernet designs targeting Intel Stratix 10, Intel Arria 10, and Intel Cyclone 10 GX devices is 8 in Intel Quartus Prime software version 17.1 onwards.
- Added a note to the description of Transceiver type parameter to clarify on the performance risk when using Triple-Speed Ethernet IP variant with LVDS I/O for PMA implementation in Intel Arria 10 devices for Intel Quartus Prime software versions 17.0.2 and earlier.
- Updated Figure: Hardware Multicast Address Resolution Engine
- Updated the "PCS Transmit and Receive Latency" table:
- Added PCS transmit and receive latency for Intel Stratix 10 and Intel Cyclone 10 GX devices.
- Added a footnote under the Latency (Clock Cycles) column to clarify that the latency numbers are from simulation.
- Updated the description in the CRC Checking topic.
- Updated the Configuration Register Space section:
- Updated the "IEEE 1588v2 Feature PMA Delay—Hardware" table to include digital delay information for Intel Arria 10 devices.
- Updated the "IEEE 1588v2 Feature LVDS I/O Delay—Hardware" table to include digital delay information for Intel Arria 10 and Intel Stratix 10 devices.
- Updated the description of the MAC and PCS With LVDS Soft-CDR I/O topic: Added a note to clarify on the performance risk when using Triple-Speed Ethernet IP variant with LVDS I/O for PMA implementation in Intel Arria 10 devices for Intel Quartus Prime software versions 17.0.2 and earlier.
- Added a note to the Sharing PLLs in Devices with LVDS Soft-CDR I/O topic.
- Updated the Creating Clock Constraints topic: Added a note to clarify that the derive_pll_clocks command is not supported in Intel Stratix 10 devices.
- Made editorial updates throughout the document.
|
| March 2017 |
2017.03.08 |
- Updated the note below Figure 6-5 in the 10/100/1000 Ethernet MAC with 1000BASE-X/SGMII PCS and Embedded PMA Signals topic.
- Updated the Arria 10 and Cyclone V Resource Utilization tables to include information about 10/100/1000-Mbps Ethernet MAC and 1000BASE-X/SGMII PCS MegaCore Function.
- Updated the link in the Related Information section for the Altera IEEE 1588v2 Features topic.
- Editorial fix to the notes in Figures 6-5, 6-6, 6-7, and 7-2.
|
| January 2017 |
2017.01.05 |
- Added ordering code IP-TRIETHERNETF for IEEE 1588v2 and product ID(s) 00BD and 0104 for Triple-Speed Ethernet and IEEE 1588v2.
|
| January 2017 |
2017.01.05 |
Corrected typo in the Configuration Register Space topic. |
| October 2016 |
2016.10.31 |
- Corrected the Device Family Support topic to include all supported devices, including devices that do not have the 1588 feature support.
- Removed mention of read_timeout in the topic about MAC reset.
- Updated the description of DISABLE_READ_TIMEOUT in the topic about the command_config register.
- Removed read_timeout and disable_read_timeout registers from the table that lists the PCS configuration registers.
|
| May 2016 |
2016.05.02 |
- Updated the Device Family Support topic.
- Updated the Performance and Resource Utilization topic.
- Updated the Release Information topic.
- Removed the Design Example topic and the appendices that described the design components, Time-of-Day (ToD) Clock, ToD Synchronizer, and Packet Classifier. Added a link to the application note for the design example.
- Added the Document Archives topic that lists documents for the past releases.
- Removed the PMA and LVDS I/O Delay—Simulation Model tables from the IEEE 1588v2 Feature PMA Delay topic because simulation data is not deterministic.
|
| November 2015 |
2015.11.02 |
- ToD Clock chapter:
- Updated the device family support.
- Added a new parameter—PERIOD_CLOCK_FREQUENCY.
- Updated the CSR description for SecondsH, SecondsL, NanoSec, Period, AdjustPeriod, DriftAdjust, and DriftAdjustRate.
- ToD Synchronizer chapter:
- Updated the device family support.
- Changed the frequency range to 390.625 MHz (from 312.5 MHz)
- Added a new table—"Sampling Clock Frequency According to the Selected Parameter Settings".
- Updated the "Settings to Achieve the Recommended Factors for Stratix V PLL" table with more sampling clock factors.
- Updated the parameter value of SYNC_MODE to "Between 0 to 15" (from "Between 0 to 6").
- Added a new parameter—SAMPLE_SIZE.
- Updated the description for tx_serial_clk to state that the clock frequency is 1250 MHz.
- Changed instances of Quartus II to Quartus Prime.
|
| June 2015 |
2015.06.15 |
- Added a new parameter, , in the Core Configuration Parameters table.
- Added description for new signals—tx_clkena, rx_clkena, and led_panel_link.
- Added Qsys-equivalent signal names for the following signals:Use clock enable for MAC
- control_port_clock_connection: clk
- pcs_mac_tx_clock_connection: tx_clk
- pcs_mac_rx_clock_connection: rx_clk
- receive_clock_connection: ff_rx_clk
- transmit_clock_connection: ff_tx_clk
- Revised the Command_config register field descriptions for bits 0, 1, and 13.
- Corrected the Command_config register setting for Enable MAC Transmit and Receive Datapath register initialization sequence from 0x00802223 to 0x00800223.
- Corrected the bit width for pkt_class_dataUse clock enable signal in the following timing diagrams:
- Receive Operation—MAC Without Internal FIFO Buffers.
- Invalid Length Error During Receive Operation—MAC Without Internal FIFO Buffers.
- Updated the following sections to indicate that the reconfiguration signals are not present in variations targeting Arria 10, Stratix V, Arria V, and Cyclone V devices with GX transceivers.
- note in 10/100/1000 Ethernet MAC with 1000BASE-X/SGMII PCS and Embedded PMA Signals
- SERDES control signals description in SERDES Control Signals.
- note in 10/100/1000 Multiport Ethernet MAC with 1000BASE-X/SGMII PCS and Embedded PMA Signals
- Sharing Transceiver Quads
- Updated the description for Extended Statistics Counters (0x3C – 0x3E) to state the specific order for reading counters.
- Removed "10/100/1000-Mbps MAC with 1000BASE-X/SGMII PCS" configuration from the list of supported configurations in IEEE 1588v2 feature.
- Added a new topic—Using ToD Clock SecondsH, SecondsL, and NanoSecRegisters.
|
| June 2014 |
14.0 |
- Added a link to the Altera website that provides the latest device support information for Altera IP.
- Added a note in PCS/Transceiver Options—You must configure the Arria 10 Transceiver ATX PLL output clock frequency to 1250.0 MHz when using the Arria 10 Transceiver Native PHY with the Triple-Speed Ethernet IP core.
- Added MAC Error Correction Code (ECC) section.
- Added new support configuration for IEEE 1588v2 feature.
- Updated the tx_period and rx_period register bits in IEEE 1588v2 Feature (Dword Offset 0xD0 - 0xD6).
- Updated the timing adjustment for the IEEE 1588v2 feature PMA delay in IEEE 1588v2 Feature PMA Delay.
- Revised the control interface signal names to reg_rd, reg_data_in, reg_wr, reg_busy, and reg_addr in MAC Control Interface.
- Added ECC status signals in ECC Status Signals and ECC Status Signals .
- Added Arria 10 Transceiver Native PHY signals in Transceiver Native PHY Signals.
- Added Transceiver Native PHY signal in Transceiver Native PHY Signals.
- Updated the following the signal diagrams:
- 10/100/1000 Ethernet MAC Signals
- 1000BASE-X/SGMII PCS Function Signals
- 10/100/1000 Ethernet MAC with 1000BASE-X/SGMII PCS Signals
- 10/100/1000 Multiport Ethernet MAC Function without Internal FIFO Buffers, with IEEE 1588v2, 1000BASE-X/SGMII PCS and Embedded PMA Signals
- Added IEEE 1588v2 feature PHY path delay interface signals inIEEE 1588v2 PHY Path Delay Interface Signals .
- Updated the Period and AdjustPeriod register bits in ToD Clock Configuration Register Space.
- Added two new conditions that the ToD synchronizer module supports in ToD Synchronizer chapter.
- Added three new recommended sampling clock frequencies in ToD Synchronizer chapter.
- Added a new setting of 32/63 in ToD Synchronizer Block.
- Updated the SYNC_MODE parameter value and description in ToD Synchronizer Parameter Settings.
|
| December 2013 |
13.1 |
- Added support for Arria 10 device.
- Added device family support list for IEEE 1588v2 variant.
- Updated the PCS/Transceiver options parameters in PCS/Transceiver Options .
- Updated the bit order in SGMII MAC Mode Auto Negotiation , SGMII PHY Mode Auto Negotiation and If Mode Register (Word Offset 0x14).
- Added information on how to view all the signal names when implementing the IP in Qsys in Interface Signals.
- Added a section about exposed ports in the new user interface in Design Considerations.
|
| May 2013 |
13.0 |
- Updated the MegaWizard Plug-In Manager flow in Getting Started with Altera IP Cores.
- Added information about generating a design example and simulation testbench in Generating a Design Example or Simulation Model.
- Updated the list of Quartus II generated files.
- Added information about the recommended pin assignments in Design Constraint File No Longer Generated.
- Updated the MegaCore parameter names and description in Parameter Settings.
- Updated the IEEE 1588v2 feature list in Functional Descriptions .
- Updated the SGMII auto-negotiation description in Functional Descriptions.
- Added information about the IEEE 1588v2 feature PMA delay in IEEE 1588v2 Feature PMA Delay.
- Updated the Multiport Ethernet MAC with IEEE 1588v2, 1000BASE-X/SGMII PCS and Embedded PMA Signals.
- Updated the IEEE 1588v2 timestamp signal names.
- Added timing diagrams for IEEE 1588v2 timestamp signals.
- Added a section about migrating existing design to the Quartus II software new MegaCore user interface in Design Considerations.
- Updated Timing Constraints chapter, to describe the new timing constraint files and the recommended clock input frequency for each MegaCore Function variant.
- Added information about the simulation model files generated using IEEE simulation encryption in Simulation Model Files.
- Updated the jumbo frames file directory in Using Jumbo Frames.
- Updated the ToD configuration parameters in ToD Clock Parameter Setting and ToD interface signals, ToD Clock Avalon-ST Transmit Interface Signals and ToD Clock Avalon-MM Control Interface Signals.
- Added information to describe the ToD’s drift adjustment in the Adjusting ToD Clock Drift.
- Added ToD Synchronizer and Packet Classifier chapters.
- Removed SOPC Builder information.
|
| January 2013 |
12.1 |
- Added Altera IEEE 1588v2 Feature section in Chapter 4.
- Added information for the following GUI parameters: Enable timestamping, Enable PTP 1-step clock, and Timestamp fingerprint width in “Timestamp Options”.
- Added MAC registers with IEEE 1588v2 feature.
- Added IEEE 1588v2 feature signals tables.
- Added Triple-Speed Ethernet with IEEE 1588v2 Design Example section.
- Added Time-of-Day Clock section.
|
| June 2012 |
12.0 |
- Added support for Cyclone V.
- Updated the Congestion and Flow Control section in Chapter 4.
- Added Register Initialization section in Chapter 5.
- Added holdoff_quant register description.
- Added UNIDIRECTIONAL_ENABLE bit description.
- Revised and moved the section on Timing Constraint to a new chapter.
- Added information about how to customize the SDC file in Chapter 8.
- Added Pause Frame Generation section.
|
| November 2011 |
11.1 |
- Added support for Arria V.
- Revised the Device Family Support section in Chapter 1.
- Added disable_read_timeout and read_timeout registers at address 0x15 and 0x16.
|
| June 2011 |
11.0 |
- Updated support for Cyclone IV GX, Cyclone III LS, Aria II GZ, HardCopy IV GX/E and HardCopy III E devices.
- Revised Performance and Resource Utilization section in Chapter 1.
- Updated Chapter 3 to include Qsys System Integration Tool Design Flow.
- Added Transmit and Receive Latencies section in Chapter 4.
- Updated all MAC register address to dbyte addressing.
|
| December 2010 |
10.1 |
- Added support for Arria II GZ.
- Added a new parameter, Starting Channel Number.
- Streamlined the contents and document organization.
|
| August 2010 |
10.0 |
- Added support for Stratix V.
- Revised the nomenclature of device support types.
- Added chapter 5, Design Considerations. Moved the Clock Distribution section to this chapter and renamed it to Optimizing Clock Resources in Multiport MAC and PCS with Embedded PMA. Added sections on PLL Sharing and Transceiver Quad Sharing.
- Updated the description of Enable transceiver dynamic reconfiguration.
|
| November 2009 |
9.1 |
- Added support for Cyclone IV, Hardcopy III, and Hardcopy IV, and updated support for Hardcopy II to full.
- Updated chapter 1 to include a feature comparison between 10/100/1000 Ethernet MAC and small MAC.
- Updated chapter 4 to revise the 10/100/1000 Ethernet MAC description, Length checking, Reset, and Control Interface sections.
|
| March 2009 |
9.0 |
- Added support for Arria II GX.
- Updated chapter 3 to include a new parameter that enables wider statistics counters.
- Updated chapter 4 to reflect support for different speed in multiport MACs and gated clocks elimination.
- Updated chapter 6 to reflect enhancements made on the device drivers.
|
| November 2008 |
8.1 |
- Updated Chapters 3 and 4 to add description on dynamic reconfiguration.
- Updated Chapter 6 to include a procedure to add unsupported PHYs.
|
| May 2008 |
8.0 |
- Revised the performance tables and device support.
- Updated Chapters 3 and 4 to include information on MAC with multi ports and without internal FIFOs.
- Revised the clock distribution section in Chapter 4.
- Reorganized Chapter 5 to remove redundant information and to include the new testbench architecture.
- Updated Chapter 6 to include new public APIs.
|
| October 2007 |
7.2 |
- Updated Chapter 1 to reflect new device support.
- Updated Chapters 3 and 4 to include information on Small MAC.
|
| May 2007 |
7.1 |
- Added Chapters 2, 3, 5 and 6.
- Updated contents to reflect changes and enhancements in the current version.
|
| March 2007 |
7.0 |
Updated signal names and description. |
| December 2006 |
6.1 |
- Global terminology changes: 1000BASE-X PCS/SGMII to 1000BASE-X/SGMII PCS, host side or client side to internal system side, HD to half-duplex.
- Initial release of document on Web.
|
| December 2006 |
6.1 |
Initial release of document on DVD. |