Triple-Speed Ethernet Intel® FPGA IP User Guide

Download PDF
ID 683402
Date 7/22/2024
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
1. About This IP 2. Getting Started with Altera IPs 3. Parameter Settings 4. Functional Description 5. Configuration Register Space 6. Interface Signals 7. Design Considerations 8. Timing Constraints 9. Testbench 10. Software Programming Interface 11. Triple-Speed Ethernet Intel® FPGA IP User Guide Archives 12. Document Revision History for the Triple-Speed Ethernet Intel® FPGA IP User Guide A. Ethernet Frame Format B. Simulation Parameters
1. About This IP x
1.1. Release Information 1.2. Device Family Support 1.3. Features 1.4. 10/100/1000 Ethernet MAC Versus Small MAC 1.5. High-Level Block Diagrams 1.6. Example Applications 1.7. IP Verification 1.8. Performance and Resource Utilization
1.7. IP Verification x
1.7.1. Optical Platform 1.7.2. Copper Platform
2. Getting Started with Altera IPs x
2.1. Design Walkthrough 2.2. Generated Files
2.1. Design Walkthrough x
2.1.1. Creating a New Quartus® Prime Project 2.1.2. Generating a Design Example or Simulation Model 2.1.3. Simulating the System 2.1.4. Compiling the Triple-Speed Ethernet Intel® FPGA IP Design 2.1.5. Programming an FPGA Device
2.2. Generated Files x
2.2.1. Design Constraint File No Longer Generated
3. Parameter Settings x
3.1. Core Configuration 3.2. Ethernet MAC Options 3.3. FIFO Options 3.4. Timestamp Options 3.5. PCS/Transceiver Options
4. Functional Description x
4.1. 10/100/1000 Ethernet MAC 4.2. 1000BASE-X/SGMII PCS With Optional Embedded PMA 4.3. Precision Time Protocol 4.4. Deterministic Latency
4.1. 10/100/1000 Ethernet MAC x
4.1.1. MAC Architecture 4.1.2. MAC Interfaces 4.1.3. MAC Transmit Datapath 4.1.4. MAC Receive Datapath 4.1.5. MAC Transmit and Receive Latencies 4.1.6. FIFO Buffer Thresholds 4.1.7. Congestion and Flow Control 4.1.8. Magic Packets 4.1.9. MAC Local Loopback 4.1.10. MAC Error Correction Code (ECC) 4.1.11. MAC Reset 4.1.12. PHY Management (MDIO) 4.1.13. Connecting MAC to External PHYs
4.1.3. MAC Transmit Datapath x
4.1.3.1. IP Payload Re-alignment 4.1.3.2. Address Insertion 4.1.3.3. Frame Payload Padding 4.1.3.4. CRC-32 Generation 4.1.3.5. Interpacket Gap Insertion 4.1.3.6. Collision Detection in Half-Duplex Mode
4.1.4. MAC Receive Datapath x
4.1.4.1. Preamble Processing 4.1.4.2. Collision Detection in Half-Duplex Mode 4.1.4.3. Address Checking 4.1.4.4. Frame Type Validation 4.1.4.5. Payload Pad Removal 4.1.4.6. CRC Checking 4.1.4.7. Length Checking 4.1.4.8. Frame Writing 4.1.4.9. IP Payload Alignment
4.1.4.3. Address Checking x
4.1.4.3.1. Unicast Address Checking 4.1.4.3.2. Multicast Address Resolution
4.1.6. FIFO Buffer Thresholds x
4.1.6.1. Receive Thresholds 4.1.6.2. Transmit Thresholds 4.1.6.3. Transmit FIFO Buffer Underflow
4.1.7. Congestion and Flow Control x
4.1.7.1. Remote Device Congestion 4.1.7.2. Receive FIFO Buffer and Local Device Congestion
4.1.8. Magic Packets x
4.1.8.1. Sleep Mode 4.1.8.2. Magic Packet Detection
4.1.12. PHY Management (MDIO) x
4.1.12.1. MDIO Connection 4.1.12.2. MDIO Frame Format
4.1.13. Connecting MAC to External PHYs x
4.1.13.1. Gigabit Ethernet 4.1.13.2. Programmable 10/100 Ethernet 4.1.13.3. Programmable 10/100/1000 Ethernet Operation
4.2. 1000BASE-X/SGMII PCS With Optional Embedded PMA x
4.2.1. 1000BASE-X/SGMII PCS Architecture 4.2.2. Transmit Operation 4.2.3. Receive Operation 4.2.4. Transmit and Receive Latencies 4.2.5. GMII Converter 4.2.6. SGMII Converter 4.2.7. Auto-Negotiation 4.2.8. Ten-bit Interface 4.2.9. PHY Loopback 4.2.10. PHY Power-Down 4.2.11. 1000BASE-X/SGMII PCS Reset
4.2.2. Transmit Operation x
4.2.2.1. Frame Encapsulation 4.2.2.2. 8b/10b Encoding
4.2.3. Receive Operation x
4.2.3.1. Comma Detection 4.2.3.2. 8b/10b Decoding 4.2.3.3. Frame De-encapsulation 4.2.3.4. Synchronization 4.2.3.5. Carrier Sense 4.2.3.6. Collision Detection
4.2.6. SGMII Converter x
4.2.6.1. Transmit 4.2.6.2. Receive
4.2.7. Auto-Negotiation x
4.2.7.1. 1000BASE-X Auto-Negotiation 4.2.7.2. SGMII Auto-Negotiation
4.2.10. PHY Power-Down x
4.2.10.1. Power-Down in PCS Variations with Embedded PMA
4.3. Precision Time Protocol x
4.3.1. IEEE 1588v2 Supported Configurations 4.3.2. IEEE 1588v2 Features 4.3.3. IEEE 1588v2 Architecture 4.3.4. IEEE 1588v2 Transmit Datapath 4.3.5. IEEE 1588v2 Receive Datapath 4.3.6. IEEE 1588v2 Frame Format
4.3.6. IEEE 1588v2 Frame Format x
4.3.6.1. PTP Frame in IEEE 802.3 4.3.6.2. PTP Frame over UDP/IPv4 4.3.6.3. PTP Frame over UDP/IPv6
5. Configuration Register Space x
5.1. MAC Configuration Register Space 5.2. PCS Configuration Register Space 5.3. Register Initialization
5.1. MAC Configuration Register Space x
5.1.1. Base Configuration Registers (Dword Offset 0x00 – 0x17) 5.1.2. Statistics Counters (Dword Offset 0x18 – 0x38) 5.1.3. Transmit and Receive Command Registers (Dword Offset 0x3A – 0x3B) 5.1.4. Supplementary Address (Dword Offset 0xC0 – 0xC7) 5.1.5. IEEE 1588v2 Feature (Dword Offset 0xD0 – 0xD6) 5.1.6. Deterministic Latency (Dword Offset 0xE1– 0xE3) 5.1.7. IEEE 1588v2 Feature PMA Delay
5.1.1. Base Configuration Registers (Dword Offset 0x00 – 0x17) x
5.1.1.1. Command_Config Register (Dword Offset 0x02)
5.2. PCS Configuration Register Space x
5.2.1. Control Register (Word Offset 0x00) 5.2.2. Status Register (Word Offset 0x01) 5.2.3. Dev_Ability and Partner_Ability Registers (Word Offset 0x04 – 0x05) 5.2.4. An_Expansion Register (Word Offset 0x06) 5.2.5. If_Mode Register (Word Offset 0x14)
5.2.3. Dev_Ability and Partner_Ability Registers (Word Offset 0x04 – 0x05) x
5.2.3.1. 1000BASE-X 5.2.3.2. SGMII MAC Mode Auto Negotiation 5.2.3.3. SGMII PHY Mode Auto Negotiation
5.3. Register Initialization x
5.3.1. Triple-Speed Ethernet System with MII/GMII or RGMII 5.3.2. Triple-Speed Ethernet System with SGMII 5.3.3. Triple-Speed Ethernet System with 1000BASE-X Interface
6. Interface Signals x
6.1. Interface Signals 6.2. Timing
6.1. Interface Signals x
6.1.1. 10/100/1000 Ethernet MAC Signals 6.1.2. 10/100/1000 Multiport Ethernet MAC Signals 6.1.3. 10/100/1000 Ethernet MAC with 1000BASE-X/SGMII PCS Signals 6.1.4. 10/100/1000 Ethernet MAC with 1000BASE-X/SGMII 2XTBI PCS and Embedded PMA Signals (E-Tile) 6.1.5. 10/100/1000 Ethernet MAC Without Internal FIFO Buffers with 1000BASE-X/SGMII 2XTBI PCS Signals 6.1.6. 10/100/1000 Ethernet MAC Without Internal FIFO Buffers with IEEE 1588v2 and 1000BASE-X/SGMII 2XTBI PCS Signals 6.1.7. 10/100/1000 Ethernet MAC Without Internal FIFO Buffers with IEEE 1588v2, 1000BASE-X/SGMII 2XTBI PCS, SGMII Bridge, and Deterministic Latency Signals 6.1.8. 10/100/1000 Multiport Ethernet MAC with 1000BASE-X/SGMII PCS Signals 6.1.9. 10/100/1000 Ethernet MAC with 1000BASE-X/SGMII TBI (LVDS I/O only) PCS Signals 6.1.10. 10/100/1000 Ethernet MAC with 1000BASE-X/SGMII PCS and Embedded PMA Signals 6.1.11. 10/100/1000 Multiport Ethernet MAC with 1000BASE-X/SGMII PCS and Embedded PMA Signals 6.1.12. 1000BASE-X/SGMII PCS Signals 6.1.13. 1000BASE-X/SGMII 2XTBI PCS Signals 6.1.14. 1000BASE-X/SGMII PCS and PMA Signals
6.1.1. 10/100/1000 Ethernet MAC Signals x
6.1.1.1. Clock and Reset Signals 6.1.1.2. Clock Enabler Signals 6.1.1.3. MAC Control Interface Signals 6.1.1.4. MAC Status Signals 6.1.1.5. MAC Receive Interface Signals 6.1.1.6. MAC Transmit Interface Signals 6.1.1.7. Pause and Magic Packet Signals 6.1.1.8. MII/GMII/RGMII Signals 6.1.1.9. PHY Management Signals 6.1.1.10. ECC Status Signals
6.1.2. 10/100/1000 Multiport Ethernet MAC Signals x
6.1.2.1. Multiport MAC Clock and Reset Signals 6.1.2.2. Multiport MAC Receive Interface Signals 6.1.2.3. Multiport MAC Transmit Interface Signals 6.1.2.4. Multiport MAC Packet Classification Signals 6.1.2.5. Multiport MAC FIFO Status Signals
6.1.3. 10/100/1000 Ethernet MAC with 1000BASE-X/SGMII PCS Signals x
6.1.3.1. TBI Interface Signals 6.1.3.2. Status LED Control Signals 6.1.3.3. SERDES Control Signals 6.1.3.4. ECC Status Signals
6.1.4. 10/100/1000 Ethernet MAC with 1000BASE-X/SGMII 2XTBI PCS and Embedded PMA Signals (E-Tile) x
6.1.4.1. GMII Clock Signals 6.1.4.2. E-Tile Transceiver Native PHY Signals
6.1.7. 10/100/1000 Ethernet MAC Without Internal FIFO Buffers with IEEE 1588v2, 1000BASE-X/SGMII 2XTBI PCS, SGMII Bridge, and Deterministic Latency Signals x
6.1.7.1. Deterministic Latency Clock Signals 6.1.7.2. Deterministic Latency Datapath Signals 6.1.7.3. Deterministic Latency Control and Status Interface Signals 6.1.7.4. Deterministic Latency Interface Signals 6.1.7.5. IEEE 1588v2 PCS TX PTP Alignment Interface Signals
6.1.9. 10/100/1000 Ethernet MAC with 1000BASE-X/SGMII TBI (LVDS I/O only) PCS Signals x
6.1.9.1. LVDS I/O Related Interface Signals
6.1.10. 10/100/1000 Ethernet MAC with 1000BASE-X/SGMII PCS and Embedded PMA Signals x
6.1.10.1. 1.25 Gbps Serial Interface 6.1.10.2. Transceiver Native PHY Signal 6.1.10.3. Arria® 10 Transceiver Native PHY Signals 6.1.10.4. SERDES Control Signals 6.1.10.5. Intel LVDS Transmitter and Receiver Soft-CDR I/O Signals
6.1.11. 10/100/1000 Multiport Ethernet MAC with 1000BASE-X/SGMII PCS and Embedded PMA Signals x
6.1.11.1. IEEE 1588v2 RX Timestamp Signals 6.1.11.2. IEEE 1588v2 TX Timestamp Signals 6.1.11.3. IEEE 1588v2 TX Timestamp Request Signals 6.1.11.4. IEEE 1588v2 TX Insert Control Timestamp Signals 6.1.11.5. IEEE 1588v2 Time-of-Day (TOD) Clock Interface Signals 6.1.11.6. IEEE 1588v2 PCS Phase Measurement Clock Signal 6.1.11.7. IEEE 1588v2 PHY Path Delay Interface Signals
6.1.12. 1000BASE-X/SGMII PCS Signals x
6.1.12.1. PCS Control Interface Signals 6.1.12.2. PCS Reset Signals 6.1.12.3. MII/GMII Clocks and Clock Enablers 6.1.12.4. GMII 6.1.12.5. MII 6.1.12.6. SGMII Status Signals
6.1.13. 1000BASE-X/SGMII 2XTBI PCS Signals x
6.1.13.1. Clock Enablers 6.1.13.2. PCS Reset Signals 6.1.13.3. TBI Interface Signals
6.2. Timing x
6.2.1. Avalon Streaming Receive Interface 6.2.2. Avalon Streaming Transmit Interface 6.2.3. GMII Transmit 6.2.4. GMII Receive 6.2.5. RGMII Transmit 6.2.6. RGMII Receive 6.2.7. MII Transmit 6.2.8. MII Receive 6.2.9. IEEE 1588v2 Timestamp
7. Design Considerations x
7.1. Optimizing Clock Resources in Multiport MAC with PCS and Embedded PMA 7.2. Sharing PLLs in Devices with LVDS Soft-CDR I/O 7.3. Sharing PLLs in Devices with GIGE PHY 7.4. Sharing Transceiver Quads 7.5. Migrating From Old to New User Interface For Existing Designs 7.6. Clocking Scheme of MAC with 2XTBI PCS and Embedded PMA
7.1. Optimizing Clock Resources in Multiport MAC with PCS and Embedded PMA x
7.1.1. MAC and PCS With GX Transceivers 7.1.2. MAC and PCS With LVDS Soft-CDR I/O
7.5. Migrating From Old to New User Interface For Existing Designs x
7.5.1. Exposed Ports in the New User Interface
8. Timing Constraints x
8.1. Creating Clock Constraints 8.2. Recommended Clock Frequency
9. Testbench x
9.1. Triple-Speed Ethernet Testbench Architecture 9.2. Testbench Components 9.3. Testbench Verification 9.4. Testbench Configuration 9.5. Test Flow 9.6. Simulation Model
9.6. Simulation Model x
9.6.1. Generate the Simulation Model 9.6.2. Simulate the IP 9.6.3. Simulation Model Files
10. Software Programming Interface x
10.1. Driver Architecture 10.2. Directory Structure 10.3. PHY Definition 10.4. Using Multiple SG-DMA Descriptors 10.5. Using Jumbo Frames 10.6. API Functions 10.7. Constants
10.6. API Functions x
10.6.1. alt_tse_mac_get_common_speed() 10.6.2. alt_tse_mac_set_common_speed() 10.6.3. alt_tse_phy_add_profile() 10.6.4. alt_tse_system_add_sys() 10.6.5. triple_speed_ethernet_init() 10.6.6. tse_mac_close() 10.6.7. tse_mac_raw_send() 10.6.8. tse_mac_setGMII mode() 10.6.9. tse_mac_setMIImode() 10.6.10. tse_mac_SwReset()
A. Ethernet Frame Format x
A.1. Basic Frame Format A.2. VLAN and Stacked VLAN Frame Format A.3. Pause Frame Format
A.3. Pause Frame Format x
A.3.1. Pause Frame Generation
B. Simulation Parameters x
B.1. Functionality Configuration Parameters B.2. Test Configuration Parameters
1. About This IP
2. Getting Started with Altera IPs
3. Parameter Settings
4. Functional Description
5. Configuration Register Space
6. Interface Signals
7. Design Considerations
8. Timing Constraints
9. Testbench
10. Software Programming Interface
11. Triple-Speed Ethernet Intel® FPGA IP User Guide Archives
12. Document Revision History for the Triple-Speed Ethernet Intel® FPGA IP User Guide
A. Ethernet Frame Format
B. Simulation Parameters

5.1.1.1. Command_Config Register (Dword Offset 0x02)

Figure 44. Command_Config Register Fields


At the minimum, you must configure the TX_ENA and RX_ENA bits to 1 to start the MAC operations. When configuring the command_config register, Altera recommends that you configure the TX_ENA and RX_ENA bits the last because the MAC immediately starts its operations once these bits are set to 1.

Table 39.  Command_Config Register Field Descriptions
Bit(s) Name R/W Description HW Reset
0 TX_ENA RW Transmit enable. Set this bit to 1 to enable the transmit datapath. The MAC clears this bit following a hardware or software reset. See the SW_RESET bit description. 0
1 RX_ENA RW Receive enable. Set this bit to 1 to enable the receive datapath. The MAC clears this bit following a hardware or software reset. See the SW_RESET bit description. 0
2 XON_GEN RW Pause frame generation. When you set this bit to 1, the MAC generates a pause frame with a pause quanta of 0, independent of the status of the receive FIFO buffer. 0
3 ETH_SPEED RW Ethernet speed control.
  • Set this bit to 1 to enable gigabit Ethernet operation. The set_1000 signal is masked and does not affect the operation.
  • If you set this bit to 0, gigabit Ethernet operation is enabled only if the set_1000 signal is asserted. Otherwise, the MAC operates in 10/100 Mbps Ethernet mode.

When the MAC operates in gigabit mode, the eth_mode signal is asserted. This bit is not available in the small MAC variation.

0
4 PROMIS_EN RW Promiscuous enable. Set this bit to 1 to enable promiscuous mode. In this mode, the MAC receives all frames without address filtering. 0
5 PAD_EN RW Padding removal on receive. Set this bit to 1 to remove padding from receive frames before the MAC forwards the frames to the user application. This bit has no effect on transmit frames.

This bit is not available in the small MAC variation.

0
6 CRC_FWD RW CRC forwarding on receive.
  • Set this bit to 1 to forward the CRC field to the user application.
  • Set this bit to 0 to remove the CRC field from receive frames before the MAC forwards the frame to the user application.
  • The MAC ignores this bit when it receives a padded frame and the PAD_EN bit is 1. In this case, the MAC checks the CRC field and removes the checksum and padding from the frame before forwarding the frame to the user application.
0
7 PAUSE_FWD RW Pause frame forwarding on receive.
  • Set this bit to 1 to forward receive pause frames to the user application.
  • Set this bit to 0 to terminate and discard receive pause frames.
0
8 PAUSE_IGNORE RW Pause frame processing on receive.
  • Set this bit to 1 to ignore receive pause frames.
  • Set this bit to 0 to process receive pause frames. The MAC suspends transmission for an amount of time specified by the pause quanta.
0
9 TX_ADDR_INS RW MAC address on transmit.
  • Set this bit to 1 to overwrite the source MAC address in transmit frames received from the user application with the MAC primary or supplementary address configured in the registers. The TX_ADDR_SEL bit determines the address selection.
  • Set this bit to 0 to retain the source MAC address in transmit frames received from the user application.
0
10 HD_ENA RW Half-duplex enable.
  • Set this bit to 1 to enable half-duplex.
  • Set this bit to 0 to enable full-duplex.
  • The MAC ignores this bit if you set the ETH_SPEED bit to 1.
0
11 EXCESS_COL RO Excessive collision condition.
  • The MAC sets this bit to 1 when it discards a frame after detecting a collision on 16 consecutive frame retransmissions.
  • The MAC clears this bit following a hardware or software reset. See the SW_RESET bit description.
0
12 LATE_COL RO Late collision condition.
  • The MAC sets this bit to 1 when it detects a collision after transmitting 64 bytes and discards the frame.
  • The MAC clears this bit following a hardware or software reset. See the SW_RESET bit description.
0
13 SW_RESET RW Software reset. Set this bit to 1 to trigger a software reset. The MAC clears this bit when it completes the software reset sequence.

When software reset is triggered, the MAC completes the current transmission or reception, and subsequently disables the transmit and receive logic, flushes the receive FIFO buffer, and resets the statistics counters.

0
14 MHASH_SEL RW Hash-code mode selection for multicast address resolution.
  • Set this bit to 0 to generate the hash code from the full 48-bit destination address.
  • Set this bit to 1 to generate the hash code from the lower 24 bits of the destination MAC address.
0
15 LOOP_ENA RW Local loopback enable. Set this bit to 1 to enable local loopback on the RGMII/GMII/MII of the MAC. The MAC sends transmit frames back to the receive path.

This bit is not available in the small MAC variation.

0
16 – 18 TX_ADDR_SEL[2:0] RW Source MAC address selection on transmit. If you set the TX_ADDR_INS bit to 1, the value of these bits determines the MAC address the MAC selects to overwrite the source MAC address in frames received from the user application.
  • 000 = primary address configured in the mac_0 and mac_1 registers.
  • 100 = supplementary address configured in the smac_0_0 and smac_0_1 registers.
  • 101 = supplementary address configured in the smac_1_0 and smac_1_1 registers.
  • 110 = supplementary address configured in the smac_2_0 and smac_2_1 registers.
  • 111 = supplementary address configured in the smac_3_0 and smac_3_1 registers.
000
19 MAGIC_ENA RW Magic packet detection. Set this bit to 1 to enable magic packet detection.

This bit is not available in the small MAC variation.

0
20 SLEEP RW Sleep mode enable. When the MAGIC_ENA bit is 1, set this bit to 1 to put the MAC to sleep and enable magic packet detection.

This bit is not available in the small MAC variation.

0
21 WAKEUP RO Node wake-up request. Valid only when the MAGIC_ENA bit is 1.
  • The MAC sets this bit to 1 when a magic packet is detected.
  • The MAC clears this bit when the SLEEP bit is set to 0.
0
22 XOFF_GEN RW Pause frame generation. Set this bit to 1 to generate a pause frame independent of the status of the receive FIFO buffer. The MAC sets the pause quanta field in the pause frame to the value configured in the pause_quant register. 0
23 CNTL_FRM_ENA RW MAC control frame enable on receive.
  • Set this bit to 1 to accept control frames other than pause frames (opcode = 0x0001) and forward them to the user application.
  • Set this bit to 0 to discard control frames other than pause frames.
0
24 NO_LGTH_CHECK RW Payload length check on receive.
  • Set this bit to 0 to check the actual payload length of receive frames against the length/type field in receive frames.
  • Set this bit to 1 to omit length checking.

This bit is not available in the small MAC variation

0

1 (for small MAC variation)
25 ENA_10 RW 10-Mbps interface enable. Set this bit to 1 to enable the 10-Mbps interface. The MAC asserts the ena_10 signal when you enable the 10-Mbps interface. You can also enable the 10-Mbps interface by asserting the set_10 signal. 0
26 RX_ERR_DISC RW Erroneous frames processing on receive.
  • Set this bit to 1 to discard erroneous frames received. This applies only when you enable store and forward operation in the receive FIFO buffer by setting the rx_section_full register to 0.
  • Set this bit to 0 to forward erroneous frames to the user application with rx_err[0] asserted.
0
27 DISABLE_READ_TIMEOUT RW

By default, this bit is set to 0. Set this bit to 1 to disable MAC configuration register read timeout.

To ensure the configuration register does not wait for read timeout when an error occurs, set this bit to 1.

0
28 – 30 Reserved — — 000
31 CNT_RESET RW Statistics counters reset. Set this bit to 1 to clear the statistics counters. The MAC clears this bit when the reset sequence completes. 0
Level Two Title