Triple-Speed Ethernet Intel® FPGA IP User Guide

ID 683402
Date 10/12/2023
Document Table of Contents

5.3.3. Triple-Speed Ethernet System with 1000BASE-X Interface

Figure 47.  Triple-Speed Ethernet System with 1000BASE-X Interface with Register Initialization Recommendation

Use the following recommended initialization sequences for the example shown in the figure above.

  1. External PHY Initialization using MDIO
  2. PCS Configuration Register Initialization
    1. Set Auto Negotiation Link Timer

      //Set Link timer to 10ms for 1000BASE-X

      link_timer (address offset 0x12) = 0x12D0

      link_timer (address offset 0x13) = 0x13

    2. Configure SGMII

      //1000BASE-X/SGMII PCS is default in 1000BASE-X Mode

      //SGMII_ENA = 0, USE_SGMII_AN = 0

      if_mode = 0x0000

    3. Enable Auto Negotiation

      //Enable Auto Negotiation

      //AUTO_NEGOTIATION_ENA = 1, Bit 6,8,13 is Read Only

      PCS Control Register = 0x1140

    4. PCS Reset

      //PCS Software reset is recommended where there any configuration changed

      //RESET = 1

      PCS Control Register = 0x9140

      Wait PCS Control Register RESET bit is clear

  3. MAC Configuration Register Initialization

If 1000BASE-X/SGMII PCS is initialized, set the ETH_SPEED (bit 3) and ENA_10 (bit 25) in command_config register to 0. If half duplex is reported in the PHY/PCS status register, set the HD_ENA (bit 10) to 1 in command_config register.