- 6.1.5. 10/100/1000 Ethernet MAC Without Internal FIFO Buffers with 1000BASE-X/SGMII 2XTBI PCS Signals
- 6.1.6. 10/100/1000 Ethernet MAC Without Internal FIFO Buffers with IEEE 1588v2 and 1000BASE-X/SGMII 2XTBI PCS Signals
B.2. Test Configuration Parameters
|Supported in configurations that contain the 10/100/1000 Ethernet MAC|
|TB_RXFRAMES||Enables local loopback on the Ethernet side (GMII/MII/RGMII). The value must always be set to 0.||0|
|TB_TXFRAMES||Specifies the number of frames to be generated by the Avalon® streaming Ethernet frame generator.||5|
|TB_RXIPG||IPG on the receive path.||12|
|TB_ENA_VAR_IPG||0: A constant IPG, TB_RXIPG, is used by the GMII/RGMII/MII Ethernet frame generator.
1: Enables variable IPG on the receive path.
|TB_LENSTART||Specifies the payload length of the first frame generated by the frame generators. The payload length of each subsequent frame is incremented by the value of TB_LENSTEP.||100|
|TB_LENSTEP||Specifies the payload length increment.||1|
|TB_LENMAX||Specifies the maximum payload length generated by the frame generators. If the payload length exceeds this value, it wraps around to TB_LENSTART. This parameter can be used to test frame length error by setting it to a value larger than the value of TB_MACLENMAX.||1500|
|TB_ENA_PADDING||0: Disables padding.
1: If the length of frames generated by the GMII/RGMII/MII Ethernet frame generator is less than the minimum frame length (64 bytes), the generator inserts padding bytes to the frames to make up the minimum length.
|TB_ENA_VLAN||0: Only basic frames are generated.
1: Enables VLAN frames generation. This value specifies the number of basic frames generated before a VLAN frame is generated followed by a stacked VLAN frame.
|TB_STOPREAD||Specifies the number of packets to be read from the receive FIFO before reading is suspended. You can use this parameter to test FIFO overflow and flow control.||0|
|TB_HOLDREAD||Specifies the number of clock cycles before the Avalon® streaming monitor stops reading from the receive FIFO.||1000|
|TB_TX_FF_ERR||0: Normal behavior.
1: Drives the Avalon® streaming error signal high to simulate erroneous frames transmission.
|TB_TRIGGERXOFF||Specifies the number of clock cycles from the start of simulation before the xoff_gen signal is driven.||0|
|TB_TRIGGERXON||Specifies the number of clock cycles from the start of simulation before the xon_gen signal is driven high.||0|
|RX_COL_FRM||Specifies which frame is received with collision. Valid in fast Ethernet and half-duplex mode only.||0|
|RX_COL_GEN||Specifies which nibble within the frame collision occurs.||0|
|TX_COL_FRM||Specifies which frame is transmitted with a collision. Valid in fast Ethernet and half-duplex mode only.||0|
|TX_COL_GEN||Specifies which nibble within the frame collision occurs on the transmit path.||0|
|TX_COL_NUM||Specifies the number of consecutive collisions during retransmission.||0|
|TX_COL_DELAY||Specifies the delay, in nibbles, between collision and retransmission.||0|
|TB_PAUSECONTROL||0: GMII frame generator does not respond to pause frames.
1: Enables flow control in the GMII frame generator.
|TB_MDIO_SIMULATION||Enable / Disable MDIO simulation.||0|
|Supported in configurations that contain the 1000BASE-X/SGMII PCS|
|TB_SGMII_HD||0: Disables half-duplex mode.
1: Enables half-duplex mode.
|TB_SGMII_1000||0: Disables gigabit operation.
1: Enables gigabit operation.
|TB_SGMII_100||0: Disables 100 Mbps operation.
1: Enables 100 Mbps operation.
|TB_SGMII_10||0: Disables 10 Mbps operation.
1: Enables 10 Mbps operation.
|TB_TX_ERR||0: Disables error generation.
1: Enables error generation.
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