- 6.1.5. 10/100/1000 Ethernet MAC Without Internal FIFO Buffers with 1000BASE-X/SGMII 2XTBI PCS Signals
- 6.1.6. 10/100/1000 Ethernet MAC Without Internal FIFO Buffers with IEEE 1588v2 and 1000BASE-X/SGMII 2XTBI PCS Signals
1.1. Release Information
Intel® FPGA IP versions match the Intel® Quartus® Prime Design Suite software versions until v19.1. Starting in Intel® Quartus® Prime Design Suite software version 19.2, Intel® FPGA IP has a new versioning scheme.
The Intel® FPGA IP version (X.Y.Z) number can change with each Intel® Quartus® Prime software version. A change in:
- X indicates a major revision of the IP. If you update the Intel® Quartus® Prime software, you must regenerate the IP.
- Y indicates the IP includes new features. Regenerate your IP to include these new features.
- Z indicates the IP includes minor changes. Regenerate your IP to include these changes.
|Intel® Quartus® Prime Version||22.4|
|Ordering Code|| Triple-Speed Ethernet: IP-TRIETHERNET
IEEE 1588v2 for Triple-Speed Ethernet: IP-TRIETHERNETF
|Product ID(s)|| Triple-Speed Ethernet: 00BD
IEEE 1588v2 for Triple-Speed Ethernet: 0104
Intel verifies that the current version of the Intel® Quartus® Prime software compiles the previous version of each IP. The Intel® FPGA IP Release Notes report any exceptions to this verification. Intel does not verify compilation with IP versions older than one release.
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