1. About This IP 2. Getting Started with Intel FPGA IPs 3. Parameter Settings 4. Functional Description 5. Configuration Register Space 6. Interface Signals 7. Design Considerations 8. Timing Constraints 9. Testbench 10. Software Programming Interface 11. Triple-Speed Ethernet Intel® FPGA IP User Guide Archives 12. Document Revision History for the Triple-Speed Ethernet Intel® FPGA IP User Guide A. Ethernet Frame Format B. Simulation Parameters
4.1.1. MAC Architecture 4.1.2. MAC Interfaces 4.1.3. MAC Transmit Datapath 4.1.4. MAC Receive Datapath 4.1.5. MAC Transmit and Receive Latencies 4.1.6. FIFO Buffer Thresholds 4.1.7. Congestion and Flow Control 4.1.8. Magic Packets 4.1.9. MAC Local Loopback 4.1.10. MAC Error Correction Code (ECC) 4.1.11. MAC Reset 4.1.12. PHY Management (MDIO) 4.1.13. Connecting MAC to External PHYs
4.2.1. 1000BASE-X/SGMII PCS Architecture 4.2.2. Transmit Operation 4.2.3. Receive Operation 4.2.4. Transmit and Receive Latencies 4.2.5. GMII Converter 4.2.6. SGMII Converter 4.2.7. Auto-Negotiation 4.2.8. Ten-bit Interface 4.2.9. PHY Loopback 4.2.10. PHY Power-Down 4.2.11. 1000BASE-X/SGMII PCS Reset
5.1.1. Base Configuration Registers (Dword Offset 0x00 – 0x17) 5.1.2. Statistics Counters (Dword Offset 0x18 – 0x38) 5.1.3. Transmit and Receive Command Registers (Dword Offset 0x3A – 0x3B) 5.1.4. Supplementary Address (Dword Offset 0xC0 – 0xC7) 5.1.5. IEEE 1588v2 Feature (Dword Offset 0xD0 – 0xD6) 5.1.6. Deterministic Latency (Dword Offset 0xE1– 0xE3) 5.1.7. IEEE 1588v2 Feature PMA Delay
6.1.1. 10/100/1000 Ethernet MAC Signals 6.1.2. 10/100/1000 Multiport Ethernet MAC Signals 6.1.3. 10/100/1000 Ethernet MAC with 1000BASE-X/SGMII PCS Signals 6.1.4. 10/100/1000 Ethernet MAC with 1000BASE-X/SGMII 2XTBI PCS and Embedded PMA Signals (E-Tile) 6.1.5. 10/100/1000 Ethernet MAC Without Internal FIFO Buffers with 1000BASE-X/SGMII 2XTBI PCS Signals 6.1.6. 10/100/1000 Ethernet MAC Without Internal FIFO Buffers with IEEE 1588v2 and 1000BASE-X/SGMII 2XTBI PCS Signals 6.1.7. 10/100/1000 Ethernet MAC Without Internal FIFO Buffers with IEEE 1588v2, 1000BASE-X/SGMII 2XTBI PCS, SGMII Bridge, and Deterministic Latency Signals 6.1.8. 10/100/1000 Multiport Ethernet MAC with 1000BASE-X/SGMII PCS Signals 6.1.9. 10/100/1000 Ethernet MAC with 1000BASE-X/SGMII TBI (LVDS I/O only) PCS Signals 6.1.10. 10/100/1000 Ethernet MAC with 1000BASE-X/SGMII PCS and Embedded PMA Signals 6.1.11. 10/100/1000 Multiport Ethernet MAC with 1000BASE-X/SGMII PCS and Embedded PMA Signals 6.1.12. 1000BASE-X/SGMII PCS Signals 6.1.13. 1000BASE-X/SGMII 2XTBI PCS Signals 6.1.14. 1000BASE-X/SGMII PCS and PMA Signals
22.214.171.124. Clock and Reset Signals 126.96.36.199. Clock Enabler Signals 188.8.131.52. MAC Control Interface Signals 184.108.40.206. MAC Status Signals 220.127.116.11. MAC Receive Interface Signals 18.104.22.168. MAC Transmit Interface Signals 22.214.171.124. Pause and Magic Packet Signals 126.96.36.199. MII/GMII/RGMII Signals 188.8.131.52. PHY Management Signals 184.108.40.206. ECC Status Signals
220.127.116.11. IEEE 1588v2 RX Timestamp Signals 18.104.22.168. IEEE 1588v2 TX Timestamp Signals 22.214.171.124. IEEE 1588v2 TX Timestamp Request Signals 126.96.36.199. IEEE 1588v2 TX Insert Control Timestamp Signals 188.8.131.52. IEEE 1588v2 Time-of-Day (TOD) Clock Interface Signals 184.108.40.206. IEEE 1588v2 PCS Phase Measurement Clock Signal 220.127.116.11. IEEE 1588v2 PHY Path Delay Interface Signals
7.1. Optimizing Clock Resources in Multiport MAC with PCS and Embedded PMA 7.2. Sharing PLLs in Devices with LVDS Soft-CDR I/O 7.3. Sharing PLLs in Devices with GIGE PHY 7.4. Sharing Transceiver Quads 7.5. Migrating From Old to New User Interface For Existing Designs 7.6. Clocking Scheme of MAC with 2XTBI PCS and Embedded PMA
10.6.1. alt_tse_mac_get_common_speed() 10.6.2. alt_tse_mac_set_common_speed() 10.6.3. alt_tse_phy_add_profile() 10.6.4. alt_tse_system_add_sys() 10.6.5. triple_speed_ethernet_init() 10.6.6. tse_mac_close() 10.6.7. tse_mac_raw_send() 10.6.8. tse_mac_setGMII mode() 10.6.9. tse_mac_setMIImode() 10.6.10. tse_mac_SwReset()
- 6.1.5. 10/100/1000 Ethernet MAC Without Internal FIFO Buffers with 1000BASE-X/SGMII 2XTBI PCS Signals
- 6.1.6. 10/100/1000 Ethernet MAC Without Internal FIFO Buffers with IEEE 1588v2 and 1000BASE-X/SGMII 2XTBI PCS Signals
6.1.7. 10/100/1000 Ethernet MAC Without Internal FIFO Buffers with IEEE 1588v2, 1000BASE-X/SGMII 2XTBI PCS, SGMII Bridge, and Deterministic Latency Signals
3.1. Core Configuration
||Determines the primary blocks to include in the variation.|
|Enable ECC protection||On/Off||Turn on this option to enable ECC protection for internal memory blocks.|
||Determines the Ethernet-side interface of the MAC block.
|Use clock enable for MAC||On/Off||Turn on this option to include clock enable signals for the MAC. This option is only applicable for 10/100/1000Mb Ethernet MAC and 1000Mb Small MAC core variations.|
|Use internal FIFO||On/Off||Turn on this option to include internal FIFO buffers in the core. You can only include internal FIFO buffers in single-port MACs.|
|Number of ports||1, 4, 8, 12, 16, 20, and 24||Specifies the number of Ethernet ports supported by the IP. This parameter is enabled if the parameter Use internal FIFO is turned off. A multiport MAC does not support internal FIFO buffers.
Note: For Intel® Quartus® Prime software version 17.1 onwards, the number of ports supported for Triple-Speed Ethernet designs targeting Intel® Stratix® 10, Intel® Arria® 10, and Intel® Cyclone® 10 GX devices is 8. This is applicable only when you select LVDS I/O for the Transceiver type option.
||This option is only available for variations that include the PCS block.
Note: There may be a performance risk if you use the Triple-Speed Ethernet Intel® FPGA IP variant with LVDS I/O for PMA implementation in the Intel® Arria® 10 devices for Intel® Quartus® Prime software version 17.0.2 and earlier. To avoid the performance risk, Intel® recommends that you regenerate the Triple-Speed Ethernet Intel® FPGA IP and recompile the design in the Intel® Quartus® Prime software version 17.1 or later. To download and install the software patch for Intel® Quartus® Prime version 17.0.2, refer to KDB link: Performance Risk Running Triple Speed Ethernet LVDS in Arria 10 Devices.
2 This variation is only supported when you select Intel® Stratix® 10 devices with E-tile transceivers or Intel® Agilex™ devices with E-tile or F-tile transceivers in the Intel® Quartus® Prime Pro Edition software.
3 You can only turn off Use internal FIFO option for this variation when you select Intel® Stratix® 10 devices with E-tile transceivers is selected starting from Intel® Quartus® Prime software version 20.4.
4 Embedded PMA is included and is not optional when you turn on the Use internal FIFO option for this variation. However, the embedded PMA is excluded when you turn off Use internal FIFO. You must manually connect the variant to the E-tile transceiver or external PHY that supports the 2XTBI interface.
5 This variation is only supported in Intel® Stratix® 10 devices.
6 Embedded PMA is excluded. You must manually connect the variant to the E-tile or external PHY that supports 2XTBI interface.
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