Triple-Speed Ethernet Intel® FPGA IP User Guide

ID 683402
Date 10/12/2023
Document Table of Contents
Give Feedback Transceiver Native PHY Signal

Table 92.  Transceiver Native PHY Signal
Name I/O Description
cdr_ref_clk_n I Port to connect the RX PLL reference clock with a frequency of 125 MHz when you enable SyncE support.