1. About This IP 2. Getting Started with Intel FPGA IPs 3. Parameter Settings 4. Functional Description 5. Configuration Register Space 6. Interface Signals 7. Design Considerations 8. Timing Constraints 9. Testbench 10. Software Programming Interface 11. Triple-Speed Ethernet Intel® FPGA IP User Guide Archives 12. Document Revision History for the Triple-Speed Ethernet Intel® FPGA IP User Guide A. Ethernet Frame Format B. Simulation Parameters
4.1.1. MAC Architecture 4.1.2. MAC Interfaces 4.1.3. MAC Transmit Datapath 4.1.4. MAC Receive Datapath 4.1.5. MAC Transmit and Receive Latencies 4.1.6. FIFO Buffer Thresholds 4.1.7. Congestion and Flow Control 4.1.8. Magic Packets 4.1.9. MAC Local Loopback 4.1.10. MAC Error Correction Code (ECC) 4.1.11. MAC Reset 4.1.12. PHY Management (MDIO) 4.1.13. Connecting MAC to External PHYs
4.2.1. 1000BASE-X/SGMII PCS Architecture 4.2.2. Transmit Operation 4.2.3. Receive Operation 4.2.4. Transmit and Receive Latencies 4.2.5. GMII Converter 4.2.6. SGMII Converter 4.2.7. Auto-Negotiation 4.2.8. Ten-bit Interface 4.2.9. PHY Loopback 4.2.10. PHY Power-Down 4.2.11. 1000BASE-X/SGMII PCS Reset
5.1.1. Base Configuration Registers (Dword Offset 0x00 – 0x17) 5.1.2. Statistics Counters (Dword Offset 0x18 – 0x38) 5.1.3. Transmit and Receive Command Registers (Dword Offset 0x3A – 0x3B) 5.1.4. Supplementary Address (Dword Offset 0xC0 – 0xC7) 5.1.5. IEEE 1588v2 Feature (Dword Offset 0xD0 – 0xD6) 5.1.6. Deterministic Latency (Dword Offset 0xE1– 0xE3) 5.1.7. IEEE 1588v2 Feature PMA Delay
6.1.1. 10/100/1000 Ethernet MAC Signals 6.1.2. 10/100/1000 Multiport Ethernet MAC Signals 6.1.3. 10/100/1000 Ethernet MAC with 1000BASE-X/SGMII PCS Signals 6.1.4. 10/100/1000 Ethernet MAC with 1000BASE-X/SGMII 2XTBI PCS and Embedded PMA Signals (E-Tile) 6.1.5. 10/100/1000 Ethernet MAC Without Internal FIFO Buffers with 1000BASE-X/SGMII 2XTBI PCS Signals 6.1.6. 10/100/1000 Ethernet MAC Without Internal FIFO Buffers with IEEE 1588v2 and 1000BASE-X/SGMII 2XTBI PCS Signals 6.1.7. 10/100/1000 Ethernet MAC Without Internal FIFO Buffers with IEEE 1588v2, 1000BASE-X/SGMII 2XTBI PCS, SGMII Bridge, and Deterministic Latency Signals 6.1.8. 10/100/1000 Multiport Ethernet MAC with 1000BASE-X/SGMII PCS Signals 6.1.9. 10/100/1000 Ethernet MAC with 1000BASE-X/SGMII TBI (LVDS I/O only) PCS Signals 6.1.10. 10/100/1000 Ethernet MAC with 1000BASE-X/SGMII PCS and Embedded PMA Signals 6.1.11. 10/100/1000 Multiport Ethernet MAC with 1000BASE-X/SGMII PCS and Embedded PMA Signals 6.1.12. 1000BASE-X/SGMII PCS Signals 6.1.13. 1000BASE-X/SGMII 2XTBI PCS Signals 6.1.14. 1000BASE-X/SGMII PCS and PMA Signals
18.104.22.168. Clock and Reset Signals 22.214.171.124. Clock Enabler Signals 126.96.36.199. MAC Control Interface Signals 188.8.131.52. MAC Status Signals 184.108.40.206. MAC Receive Interface Signals 220.127.116.11. MAC Transmit Interface Signals 18.104.22.168. Pause and Magic Packet Signals 22.214.171.124. MII/GMII/RGMII Signals 126.96.36.199. PHY Management Signals 188.8.131.52. ECC Status Signals
184.108.40.206. IEEE 1588v2 RX Timestamp Signals 220.127.116.11. IEEE 1588v2 TX Timestamp Signals 18.104.22.168. IEEE 1588v2 TX Timestamp Request Signals 22.214.171.124. IEEE 1588v2 TX Insert Control Timestamp Signals 126.96.36.199. IEEE 1588v2 Time-of-Day (TOD) Clock Interface Signals 188.8.131.52. IEEE 1588v2 PCS Phase Measurement Clock Signal 184.108.40.206. IEEE 1588v2 PHY Path Delay Interface Signals
7.1. Optimizing Clock Resources in Multiport MAC with PCS and Embedded PMA 7.2. Sharing PLLs in Devices with LVDS Soft-CDR I/O 7.3. Sharing PLLs in Devices with GIGE PHY 7.4. Sharing Transceiver Quads 7.5. Migrating From Old to New User Interface For Existing Designs 7.6. Clocking Scheme of MAC with 2XTBI PCS and Embedded PMA
10.6.1. alt_tse_mac_get_common_speed() 10.6.2. alt_tse_mac_set_common_speed() 10.6.3. alt_tse_phy_add_profile() 10.6.4. alt_tse_system_add_sys() 10.6.5. triple_speed_ethernet_init() 10.6.6. tse_mac_close() 10.6.7. tse_mac_raw_send() 10.6.8. tse_mac_setGMII mode() 10.6.9. tse_mac_setMIImode() 10.6.10. tse_mac_SwReset()
- 6.1.5. 10/100/1000 Ethernet MAC Without Internal FIFO Buffers with 1000BASE-X/SGMII 2XTBI PCS Signals
- 6.1.6. 10/100/1000 Ethernet MAC Without Internal FIFO Buffers with IEEE 1588v2 and 1000BASE-X/SGMII 2XTBI PCS Signals
6.1.7. 10/100/1000 Ethernet MAC Without Internal FIFO Buffers with IEEE 1588v2, 1000BASE-X/SGMII 2XTBI PCS, SGMII Bridge, and Deterministic Latency Signals
3.2. Ethernet MAC Options
These options are enabled when your variation includes the MAC function. In small MACs, only the following options are available:
- Enable MAC 10/100 half duplex support (10/100 Small MAC variations)
- Align packet headers to 32-bit boundary (10/100 and 1000 Small MAC variations)
|Ethernet MAC Options|
|Enable MAC 10/100 half duplex support||On/Off||Turn on this option to include support for half duplex operation on 10/100 Mbps connections.|
|Enable local loopback on MII/GMII/RGMII||On/Off||Turn on this option to enable local loopback on the MAC’s MII, GMII, or RGMII interface. If you turn on this option, the loopback function can be dynamically enabled or disabled during system operation via the MAC configuration register.|
|Enable supplemental MAC unicast addresses||On/Off||Turn on this option to include support for supplementary destination MAC unicast addresses for fast hardware-based received frame filtering.|
|Include statistics counters||On/Off||Turn on this option to include support for simple network monitoring protocol (SNMP) management information base (MIB) and remote monitoring (RMON) statistics counter registers for incoming and outgoing Ethernet packets.
By default, the width of all statistics counters are 32 bits.
|Enable 64-bit statistics byte counters||On/Off||Turn on this option to extend the width of selected statistics counters— aOctetsTransmittedOK, aOctetsReceivedOK, and etherStatsOctets—to 64 bits.|
|Include multicast hashtable||On/Off||Turn on this option to implement a hash table, a fast hardware-based mechanism to detect and filter multicast destination MAC address in received Ethernet packets.|
|Align packet headers to 32-bit boundary||On/Off||Turn on this option to include logic that aligns all packet headers to a 32-bit boundary. This helps reduce software overhead processing in realignment of data buffers.
This option is available for MAC variations with 32 bits wide internal FIFO buffers and MAC variations without internal FIFO buffers.
You must turn on this option if you intend to use the Triple-Speed Ethernet Intel® FPGA IP with the Interniche TCP/IP protocol stack.
|Enable full-duplex flow control||On/Off||Turn on this option to include the logic for full-duplex flow control that includes pause frames generation and termination.|
|Enable VLAN detection||On/Off||Turn on this option to include the logic for VLAN and stacked VLAN frame detection. When turned off, the MAC does not detect VLAN and staked VLAN frames. The MAC forwards these frames to the user application without processing them.|
|Enable magic packet detection||On/Off||Turn on this option to include logic for magic packet detection (Wake-on LAN).|
|Include MDIO module (MDC/MDIO)||On/Off||Turn on this option if you want to access external PHY devices connected to the MAC function. When turned off, the core does not include the logic or signals associated with the MDIO interface.|
|Host clock divisor||—||Clock divisor to divide the MAC control interface clock to produce the MDC clock output on the MDIO interface. The default value is 40.
For example, if the MAC control interface clock frequency is 100 MHz and the desired MDC clock frequency is 2.5 MHz, a host clock divisor of 40 should be specified.
Intel recommends that the division factor is defined such that the MDC frequency does not exceed 2.5 MHz.
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