Visible to Intel only — GUID: bhc1410931836079
Ixiasoft
Visible to Intel only — GUID: bhc1410931836079
Ixiasoft
6.1.2.5. Multiport MAC FIFO Status Signals
Signal Name | Avalon Streaming Signal Type | I/O | Description |
---|---|---|---|
rx_afull_valid_n | valid | I | Assert this signal to indicate that the fill level of the external FIFO buffer, rx_afull_data_n[1:0], is valid. |
rx_afull_data_n[1:0] | data | I | Carries the fill level of the external FIFO buffer: rx_afull_data_n[1]—Set to 1 if the external receive FIFO buffer reaches the initial warning level indicating that it is almost full. Upon detecting this, the MAC function generates pause frames. rx_afull_data_n[0]—Set to 1 if the external receive FIFO buffer reaches the critical level before it overflows. The FIFO buffer can be considered overflow if this bit is set to 1 in the middle of a packet transfer. |
rx_afull_channel[(CHANNEL_WIDTH-1):0] | channel | I | The port number the status applies to. |
rx_afull_clk | clk | I | The clock that drives the MAC FIFO status interface. |
Interface Signal | Section |
---|---|
Clock and reset signals | Clock and Reset Signals |
MAC control interface | MAC Control Interface Signals |
MAC transmit interface | MAC Transmit Interface Signals |
MAC receive interface | MAC Receive Interface Signals |
Status signals | MAC Status Signals |
Pause and magic packet signals | Pause and Magic Packet Signals |
MII/GMII/RGMII interface | MII/GMII/RGMII Signals |
PHY management signals | PHY Management Signals |
ECC status signals | ECC Status Signals |
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