Triple-Speed Ethernet Intel® FPGA IP User Guide

ID 683402
Date 10/12/2023
Public
Document Table of Contents

6.1.12.2. PCS Reset Signals

Table 106.   Reset Signals
Name I/O Description
reset_rx_clk I Active-high reset signal for PCS rx_clk clock domain. Assert this signal to reset the logic synchronized by rx_clk.
reset_tx_clk I Active-high reset signal for PCS tx_clk clock domain. Assert this signal to reset the logic synchronized by tx_clk.