Triple-Speed Ethernet Intel® FPGA IP User Guide

ID 683402
Date 7/22/2024
Public
Document Table of Contents

6.1.9. 10/100/1000 Ethernet MAC with 1000BASE-X/SGMII TBI (LVDS I/O only) PCS Signals

Figure 56. 10/100/1000 Ethernet MAC with 1000BASE-X/SGMII TBI (LCDS I/O only) PCS Signals
Table 90.  References
Interface Signal Section
Clock and reset signals Clock and Reset Signals (with FIFO)

Multiport MAC Clock and Reset Signals (without FIFO)

MAC control interface MAC Control Interface Signals
MAC transmit interface MAC Transmit Interface Signals (with FIFO)

Multiport MAC Transmit Interface Signals (without FIFO)

MAC receive interface MAC Receive Interface Signals (with FIFO)

Multiport MAC Receive Interface Signals (without FIFO)

MAC packet classification signals Multiport MAC Packet Classification Signals
MAC FIFO status signals Multiport MAC FIFO Status Signals
Pause and magic packet signals Pause and Magic Packet Signals
PHY management signals PHY Management Signals
Ten-bit interface signals TBI Interface Signals
Status LED control signals Status LED Control Signals
Ten-bit converter interface signals TBI Converter Interface Signals