Triple-Speed Ethernet Intel® FPGA IP User Guide

ID 683402
Date 10/12/2023
Public
Document Table of Contents
Give Feedback

6.1.4.1. GMII Clock Signals

Table 79.  GMII Clocks
Name I/O Description
rx_clk_125 I 125 MHz receive clock for the RX datapath on MAC side
tx_clk_125 I 125 MHz transmit clock for the TX datapath on MAC side.
rx_clk_62_5

(In Platform Designer: pcs_receive_clock_half_connection)

I 62.5 MHz receive clock for the RX datapath on PCS side.

Intel® recommends that this clock and rx_clk_125 share the same clock source. This clock must be synchronous to rx_clk_125. Their rising edges must align and must have 0 ppm and phase shift.

tx_clk_62_5

(In Platform Designer: pcs_transmit_clock_half_connection)

I 62.5 MHz transmit clock for the TX datapath on PCS side.

Intel® recommends that this clock and tx_clk_125 share the same clock source. This clock must be synchronous to tx_clk_125. Their rising edges must align and must have 0 ppm and phase shift.

For more information about the clock signals, refer to Clocking Scheme of MAC with 2XTBI PCS and Embedded PMA.