- 6.1.5. 10/100/1000 Ethernet MAC Without Internal FIFO Buffers with 1000BASE-X/SGMII 2XTBI PCS Signals
- 6.1.6. 10/100/1000 Ethernet MAC Without Internal FIFO Buffers with IEEE 1588v2 and 1000BASE-X/SGMII 2XTBI PCS Signals
3.5. PCS/Transceiver Options
|PHY ID (32 bit)||—||Configures the PHY ID of the PCS block.|
|Enable SGMII bridge||On/Off||Turn on this option to add the SGMII clock and rate-adaptation logic to the PCS block. This option allows you to configure the PCS either in SGMII mode or 1000Base-X mode. If your application only requires 1000BASE-X PCS, turning off this option reduces resource usage.
In Cyclone® IV GX devices, REFCLK[0,1] and REFCLK[4,5] cannot connect directly to the GCLK network. If you enable the SGMII bridge, you must connect ref_clk to an alternative dedicated clock input pin.
|Transceiver Options—apply only to variations that include GXB transceiver blocks|
|Export transceiver powerdown signal||On/Off||This option is not supported in Stratix® V, Arria® V, Arria® V GZ, and Cyclone® V devices.
Turn on this option to export the powerdown signal of the GX transceiver to the top-level of your design. Powerdown is shared among the transceivers in a quad. Therefore, turning on this option in multiport Ethernet configurations maximizes efficient use of transceivers within the quad.
Turn off this option to connect the powerdown signal internally to the PCS control register interface. This connection allows the host processor to control the transceiver powerdown in your system.
|Enable transceiver dynamic reconfiguration||On/Off||This option is always turned on in devices other than Arria® GX and Stratix® II GX. When this option is turned on, the IP includes the dynamic reconfiguration signals.
For designs targeting devices other than Arria® V, Cyclone® V, Stratix® V, Intel® Arria® 10, and Intel® Cyclone® 10 GX, Intel recommends that you instantiate the ALTGX_RECONFIG megafunction and connect the megafunction to the dynamic reconfiguration signals to enable offset cancellation.
For Arria® V, Cyclone® V, and Stratix® V designs, Intel recommends that you instantiate the Transceiver Reconfiguration Controller megafunction and connect the megafunction to the dynamic reconfiguration signals to enable offset cancellation. The transceivers in the Arria® V, Cyclone® V, and Stratix® V designs are configured with Intel FPGA Custom PHY IP. The Custom PHY IP requires two reconfiguration interfaces for external reconfiguration controller. For more information on the reconfiguration interfaces required, refer to the V-Series Transceiver PHY IP Core User Guide and the respective device handbook.
For more information about quad sharing considerations, refer to Sharing PLLs in Devices with GIGE PHY.
|Starting channel number||0 – 284||Specifies the channel number for the GXB transceiver block. In a multiport MAC, this parameter specifies the channel number for the first port. Subsequent channel numbers are in four increments.
In designs with multiple instances of GXB transceiver block (multiple instances of Triple-Speed Ethernet Intel® FPGA IP with GXB transceiver block or a combination of Triple-Speed Ethernet Intel® FPGA IP and other IPs), Intel recommends that you set a unique starting channel number for each instance to eliminate conflicts when the GXB transceiver blocks share a transceiver quad.
This option is not supported in Arria® V, Cyclone® V, Stratix® V, Intel® Arria® 10, and Intel® Cyclone® 10 GX devices. For these devices, the channel numbers depends on the dynamic reconfiguration controller.
|Series V GXB Transceiver Options|
|TX PLLs type||
||This option is only available for variations that include the PCS block for Stratix® V and Arria® V GZ devices.
Specifies the TX phase-locked loops (PLLs) type—CMU or ATX—in the GXB transceiver for Series V devices.
|Enable SyncE Support||On/Off||Turn on this option to enable SyncE support by separating the TX PLL and RX PLL reference clock.|
|TX PLL clock network||
||This option is only available for variations that include the PCS block for Arria® V and Cyclone® V devices.
Specifies the TX PLL clock network type.
|Intel® Arria® 10 or Intel® Cyclone® 10 GX GXB Transceiver Options|
|Enable Intel® Arria® 10 or Intel® Cyclone® 10 GX transceiver dynamic reconfiguration||On/Off||Turn on this option for the IP to include the dynamic reconfiguration signals.|
|Intel® Stratix® 10 GXB Transceiver Options|
|Enable E-tile transceiver dynamic reconfiguration||On/Off||Turn on this option for the IP to include the dynamic reconfiguration signals.|
|Intel® Stratix® 10 GXB PMA Adaptation||On/Off||Enables PMA adaptation parameter customization. For more details about PMA adaptation parameter, refer to E-Tile Transceiver PHY User Guide.|
- You must configure the Intel® Arria® 10/ Intel® Cyclone® 10 GX Transceiver ATX PLL with an output clock frequency of 1250.0 MHz (instead of applying the default value of 625 MHz) when using the Intel® Arria® 10/ Intel® Cyclone® 10 GX Transceiver Native PHY with the Triple-Speed Ethernet Intel® FPGA IP.
- The Transceiver Options and Series V GXB Transceiver Options parameters are not available in the Triple-Speed Ethernet Intel® FPGA IP parameter editor interface of the Intel® Quartus® Prime Pro Edition software version 19.2 onwards. These options are only present in the Intel® Quartus® Prime Standard Edition software.
Refer to the respective device handbook for more information on dynamic reconfiguration in Intel FPGA devices.
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