Triple-Speed Ethernet Intel® FPGA IP User Guide

ID 683402
Date 7/22/2024
Public
Document Table of Contents

7.2. Sharing PLLs in Devices with LVDS Soft-CDR I/O

For Agilex™ 7 devices, you cannot share PLLs for designs that have multiple instances of MAC and PCS with PMA or PCS with PMA variation targeting devices with LVDS soft-CDR I/O. In addition, you must adhere to the following LVDS soft-CDR placement guidelines to avoid Quartus design compilation fitter error:

  • In each GPIO bank of the Agilex™ 7 FPGA device, there are two sub-banks. The top sub-bank has pin indexes from 48-95 and supports a maximum of 4 LVDS soft-CDR I/O. The bottom sub-bank has pin indexes from 0-47 and supports a maximum of 8 LVDS soft-CDR I/O.
  • For the exact location of the LVDS soft-CDR I/O pin, refer to the Agilex™ 7 device pin-out files.
  • One Triple-Speed Ethernet IP cannot support LVDS soft-CDR I/O that has a mixture channel placement in both top and bottom sub-banks. You must constrain the LVDS soft-CDR I/O channel placement to either the top sub-bank or bottom sub-bank only.
For Stratix® 10, Arria® 10, and Cyclone® 10 GX devices, you cannot share PLLs for designs that contain multiple instances of MAC and PCS with PMA or PCS with PMA variation targeting devices with LVDS soft-CDR I/O. The Quartus® Prime software does not not merge the PLLs for these instances. Therefore, each of the design instance must be implemented in a different I/O bank with a dedicated clock path. For Stratix® 10 devices, you can choose to instantiate MAC and PCS with 1000BASE-X/SGMII TBI (LVDS I/O only) and manually connect it to an external Intel FPGA LVDS I/O to get around this PLL sharing limitation. For this implementation, multiple instances of MAC and PCS with 1000BASE-X/SGMII TBI (LVDS I/O only) can be connected to a single instance of LVDS I/O.
Figure 83. 10/100/1000Mb Ethernet MAC with 1000BASE-X/SGMII TBI (LVDS I/O only) PCS variant

For older devices, you can optimize the resource utilization by sharing the PLLs for designs that contain multiple instances of MAC and PCS with PMA or PCS with PMA variation targeting devices with LVDS soft-CDR I/O.

The Quartus® Prime software merges the PLLs for these instances if you implement the following items in your design:

  • Connect the reference clock of each instance to the same source.
  • Place the LVDS I/O pins on the same side of the FPGA.
Note: For Quartus® Prime software version 17.1 onwards, the number of ports supported for Triple-Speed Ethernet design targeting Stratix® 10, Arria® 10, and Cyclone® 10 GX devices is 8 ports per instance. Assign the number of ports supported and its reference clock to the same I/O bank as inter-bank clock sharing is not allowed.