1. About This IP 2. Getting Started with Intel FPGA IPs 3. Parameter Settings 4. Functional Description 5. Configuration Register Space 6. Interface Signals 7. Design Considerations 8. Timing Constraints 9. Testbench 10. Software Programming Interface 11. Triple-Speed Ethernet Intel® FPGA IP User Guide Archives 12. Document Revision History for the Triple-Speed Ethernet Intel® FPGA IP User Guide A. Ethernet Frame Format B. Simulation Parameters
4.1.1. MAC Architecture 4.1.2. MAC Interfaces 4.1.3. MAC Transmit Datapath 4.1.4. MAC Receive Datapath 4.1.5. MAC Transmit and Receive Latencies 4.1.6. FIFO Buffer Thresholds 4.1.7. Congestion and Flow Control 4.1.8. Magic Packets 4.1.9. MAC Local Loopback 4.1.10. MAC Error Correction Code (ECC) 4.1.11. MAC Reset 4.1.12. PHY Management (MDIO) 4.1.13. Connecting MAC to External PHYs
4.2.1. 1000BASE-X/SGMII PCS Architecture 4.2.2. Transmit Operation 4.2.3. Receive Operation 4.2.4. Transmit and Receive Latencies 4.2.5. GMII Converter 4.2.6. SGMII Converter 4.2.7. Auto-Negotiation 4.2.8. Ten-bit Interface 4.2.9. PHY Loopback 4.2.10. PHY Power-Down 4.2.11. 1000BASE-X/SGMII PCS Reset
5.1.1. Base Configuration Registers (Dword Offset 0x00 – 0x17) 5.1.2. Statistics Counters (Dword Offset 0x18 – 0x38) 5.1.3. Transmit and Receive Command Registers (Dword Offset 0x3A – 0x3B) 5.1.4. Supplementary Address (Dword Offset 0xC0 – 0xC7) 5.1.5. IEEE 1588v2 Feature (Dword Offset 0xD0 – 0xD6) 5.1.6. Deterministic Latency (Dword Offset 0xE1– 0xE3) 5.1.7. IEEE 1588v2 Feature PMA Delay
6.1.1. 10/100/1000 Ethernet MAC Signals 6.1.2. 10/100/1000 Multiport Ethernet MAC Signals 6.1.3. 10/100/1000 Ethernet MAC with 1000BASE-X/SGMII PCS Signals 6.1.4. 10/100/1000 Ethernet MAC with 1000BASE-X/SGMII 2XTBI PCS and Embedded PMA Signals (E-Tile) 6.1.5. 10/100/1000 Ethernet MAC Without Internal FIFO Buffers with 1000BASE-X/SGMII 2XTBI PCS Signals 6.1.6. 10/100/1000 Ethernet MAC Without Internal FIFO Buffers with IEEE 1588v2 and 1000BASE-X/SGMII 2XTBI PCS Signals 6.1.7. 10/100/1000 Ethernet MAC Without Internal FIFO Buffers with IEEE 1588v2, 1000BASE-X/SGMII 2XTBI PCS, SGMII Bridge, and Deterministic Latency Signals 6.1.8. 10/100/1000 Multiport Ethernet MAC with 1000BASE-X/SGMII PCS Signals 6.1.9. 10/100/1000 Ethernet MAC with 1000BASE-X/SGMII TBI (LVDS I/O only) PCS Signals 6.1.10. 10/100/1000 Ethernet MAC with 1000BASE-X/SGMII PCS and Embedded PMA Signals 6.1.11. 10/100/1000 Multiport Ethernet MAC with 1000BASE-X/SGMII PCS and Embedded PMA Signals 6.1.12. 1000BASE-X/SGMII PCS Signals 6.1.13. 1000BASE-X/SGMII 2XTBI PCS Signals 6.1.14. 1000BASE-X/SGMII PCS and PMA Signals
220.127.116.11. Clock and Reset Signals 18.104.22.168. Clock Enabler Signals 22.214.171.124. MAC Control Interface Signals 126.96.36.199. MAC Status Signals 188.8.131.52. MAC Receive Interface Signals 184.108.40.206. MAC Transmit Interface Signals 220.127.116.11. Pause and Magic Packet Signals 18.104.22.168. MII/GMII/RGMII Signals 22.214.171.124. PHY Management Signals 126.96.36.199. ECC Status Signals
188.8.131.52. IEEE 1588v2 RX Timestamp Signals 184.108.40.206. IEEE 1588v2 TX Timestamp Signals 220.127.116.11. IEEE 1588v2 TX Timestamp Request Signals 18.104.22.168. IEEE 1588v2 TX Insert Control Timestamp Signals 22.214.171.124. IEEE 1588v2 Time-of-Day (TOD) Clock Interface Signals 126.96.36.199. IEEE 1588v2 PCS Phase Measurement Clock Signal 188.8.131.52. IEEE 1588v2 PHY Path Delay Interface Signals
7.1. Optimizing Clock Resources in Multiport MAC with PCS and Embedded PMA 7.2. Sharing PLLs in Devices with LVDS Soft-CDR I/O 7.3. Sharing PLLs in Devices with GIGE PHY 7.4. Sharing Transceiver Quads 7.5. Migrating From Old to New User Interface For Existing Designs 7.6. Clocking Scheme of MAC with 2XTBI PCS and Embedded PMA
10.6.1. alt_tse_mac_get_common_speed() 10.6.2. alt_tse_mac_set_common_speed() 10.6.3. alt_tse_phy_add_profile() 10.6.4. alt_tse_system_add_sys() 10.6.5. triple_speed_ethernet_init() 10.6.6. tse_mac_close() 10.6.7. tse_mac_raw_send() 10.6.8. tse_mac_setGMII mode() 10.6.9. tse_mac_setMIImode() 10.6.10. tse_mac_SwReset()
- 6.1.5. 10/100/1000 Ethernet MAC Without Internal FIFO Buffers with 1000BASE-X/SGMII 2XTBI PCS Signals
- 6.1.6. 10/100/1000 Ethernet MAC Without Internal FIFO Buffers with IEEE 1588v2 and 1000BASE-X/SGMII 2XTBI PCS Signals
6.1.7. 10/100/1000 Ethernet MAC Without Internal FIFO Buffers with IEEE 1588v2, 1000BASE-X/SGMII 2XTBI PCS, SGMII Bridge, and Deterministic Latency Signals
7.6. Clocking Scheme of MAC with 2XTBI PCS and Embedded PMA
The following is the clocking scheme of the design that contains MAC with 2XTBI and embedded PMA on E-tile and F-tile:
- 2XTBI PCS runs on 125 MHz and 62.5 MHz clocks while the same 125 MHz clock is used by MAC.
- The 125 MHz and 62.5 MHz clocks must be synchronous, in which their rising edges must align and must have 0 ppm and phase shift.
- The E-tile Native PHY and F-tile Direct PHY are the embedded PMAs in this variant. The tx_clkout and rx_clkout on the E-tile Native PHY and F-tile Direct PHY are used as clock sources for 2XTBI PCS tbi2x_tx_clk and tbi2x_rx_clk.
- Logic is implemented in the PCS block for clock rate matching by default regardless whether the ENABLE_SGMII option is selected. Therefore, the 125 MHz and 62.5 MHz clocks do not need to be at 0 ppm in comparison with tx_clkout and rx_clkout, which are usually provided by external SERDES.
- The E-tile Native PHY and F-tile Direct PHY transceivers are driven by the 156.25 MHz clock.
- The reference clock input to the F-tile Direct PHY, tx_pll_refclk_link and rx_cdr_refclk_link, should be driven by the 156.25 MHz system PLL output.
|MAC and 2XTBI PCS with PMA||2XTBI PCS Only|
Figure 84. Clock Connectivity in MAC with 2XTBI PCS and Embedded PMA (E-Tile)
Notes to Clock Connectivity in MAC with 2XTBI PCS and Embedded PMA (E-Tile):
- Intel® recommends that the rx_clk_125, tx_clk_125, rx_clk_62_5, and tx_clk_62_5 share the same clock source.
- Therefore, Intel® recommends you use one IOPLL with two output clocks to get the 125 MHz and 62.5 MHz clocks and connect to both the TX and RX datapaths.
- rx_clkout and tx_clkout are output clocks generated by the E-tile transceiver Native PHY and F-tile transceiver Direct PHY and internally connected to tbi2x_rx_clk and tbi2x_tx_clk in the variant MAC with 2XTBI and embedded PMA.
- The reg_clk clock is internally connected to clk in the variant MAC with 2XTBI and embedded PMA. Refer to Register Interface Signals for more information about reg_clk.
- Intel recommends 156.25 MHz frequency for this clock source when the F-tile Reference and System PLL Clocks is used to drive the Triple-Speed Ethernet IP only.
23 Yes indicates that the clock is visible at the top-level design.
No indicates that the clock is not visible at the top-level design.
N/A indicates that the clock is not applicable for the given configuration.
24 Clock signals of E-tile transceiver Native PHY.
25 Clock signals of F-tile transceiver Direct PHY.
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