Triple-Speed Ethernet Intel® FPGA IP User Guide

ID 683402
Date 7/22/2024
Public

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7.6. Clocking Scheme of MAC with 2XTBI PCS and Embedded PMA

The following is the clocking scheme of the design that contains MAC with 2XTBI and embedded PMA on E-Tile:
  • 2XTBI PCS runs on 125 MHz and 62.5 MHz clocks while the same 125 MHz clock is used by MAC.
  • The 125 MHz and 62.5 MHz clocks must be synchronous, in which their rising edges must align and must have 0 ppm and phase shift.
  • The E-Tile Native PHY is the embedded PMAs in this variant. The tx_clkout and rx_clkout on the E-Tile Native PHY are used as clock sources for 2XTBI PCS tbi2x_tx_clk and tbi2x_rx_clk.
  • Logic is implemented in the PCS block for clock rate matching by default regardless whether the ENABLE_SGMII option is selected. Therefore, the 125 MHz and 62.5 MHz clocks do not need to be at 0 ppm in comparison with tx_clkout and rx_clkout, which are usually provided by external SERDES.
  • The E-Tile Native PHY transceiver is driven by the 156.25 MHz clock.
Table 119.  Clock Signals Visible at Top-Level DesignClock signals that are visible at the top-level design for each possible configuration.
Clocks Configurations 23
MAC and 2XTBI PCS with PMA 2XTBI PCS Only
clk Yes N/A
reg_clk No Yes
ff_tx_clk Yes N/A
ff_rx_clk Yes N/A
tx_clk_125 Yes Yes
rx_clk_125 Yes Yes
tx_clk_62_5 Yes Yes
rx_clk_62_5 Yes Yes
tbi2x_tx_clk No Yes
tbi2x_rx_clk No Yes
pll_refclk0 24 Yes N/A
tx_clkout 24 No N/A
rx_clkout 24 No N/A
Figure 84. Clock Connectivity in MAC with 2XTBI PCS and Embedded PMA (E-Tile)

Notes to Clock Connectivity in MAC with 2XTBI PCS and Embedded PMA (E-Tile):

  1. Altera recommends that the rx_clk_125, tx_clk_125, rx_clk_62_5, and tx_clk_62_5 share the same clock source.
  2. Therefore, Altera recommends you use one IOPLL with two output clocks to get the 125 MHz and 62.5 MHz clocks and connect to both the TX and RX datapaths.
  3. rx_clkout and tx_clkout are output clocks generated by the E-Tile transceiver Native PHY and internally connected to tbi2x_rx_clk and tbi2x_tx_clk in the variant MAC with 2XTBI and embedded PMA.
  4. The reg_clk clock is internally connected to clk in the variant MAC with 2XTBI and embedded PMA. Refer to Register Interface Signals for more information about reg_clk.
23 Yes indicates that the clock is visible at the top-level design.

No indicates that the clock is not visible at the top-level design.

N/A indicates that the clock is not applicable for the given configuration.

24 Clock signals of E-Tile transceiver Native PHY.