1. About This IP 2. Getting Started with Intel FPGA IPs 3. Parameter Settings 4. Functional Description 5. Configuration Register Space 6. Interface Signals 7. Design Considerations 8. Timing Constraints 9. Testbench 10. Software Programming Interface 11. Triple-Speed Ethernet Intel® FPGA IP User Guide Archives 12. Document Revision History for the Triple-Speed Ethernet Intel® FPGA IP User Guide A. Ethernet Frame Format B. Simulation Parameters
4.1.1. MAC Architecture 4.1.2. MAC Interfaces 4.1.3. MAC Transmit Datapath 4.1.4. MAC Receive Datapath 4.1.5. MAC Transmit and Receive Latencies 4.1.6. FIFO Buffer Thresholds 4.1.7. Congestion and Flow Control 4.1.8. Magic Packets 4.1.9. MAC Local Loopback 4.1.10. MAC Error Correction Code (ECC) 4.1.11. MAC Reset 4.1.12. PHY Management (MDIO) 4.1.13. Connecting MAC to External PHYs
4.2.1. 1000BASE-X/SGMII PCS Architecture 4.2.2. Transmit Operation 4.2.3. Receive Operation 4.2.4. Transmit and Receive Latencies 4.2.5. GMII Converter 4.2.6. SGMII Converter 4.2.7. Auto-Negotiation 4.2.8. Ten-bit Interface 4.2.9. PHY Loopback 4.2.10. PHY Power-Down 4.2.11. 1000BASE-X/SGMII PCS Reset
5.1.1. Base Configuration Registers (Dword Offset 0x00 – 0x17) 5.1.2. Statistics Counters (Dword Offset 0x18 – 0x38) 5.1.3. Transmit and Receive Command Registers (Dword Offset 0x3A – 0x3B) 5.1.4. Supplementary Address (Dword Offset 0xC0 – 0xC7) 5.1.5. IEEE 1588v2 Feature (Dword Offset 0xD0 – 0xD6) 5.1.6. Deterministic Latency (Dword Offset 0xE1– 0xE3) 5.1.7. IEEE 1588v2 Feature PMA Delay
6.1.1. 10/100/1000 Ethernet MAC Signals 6.1.2. 10/100/1000 Multiport Ethernet MAC Signals 6.1.3. 10/100/1000 Ethernet MAC with 1000BASE-X/SGMII PCS Signals 6.1.4. 10/100/1000 Ethernet MAC with 1000BASE-X/SGMII 2XTBI PCS and Embedded PMA Signals (E-Tile) 6.1.5. 10/100/1000 Ethernet MAC Without Internal FIFO Buffers with 1000BASE-X/SGMII 2XTBI PCS Signals 6.1.6. 10/100/1000 Ethernet MAC Without Internal FIFO Buffers with IEEE 1588v2 and 1000BASE-X/SGMII 2XTBI PCS Signals 6.1.7. 10/100/1000 Ethernet MAC Without Internal FIFO Buffers with IEEE 1588v2, 1000BASE-X/SGMII 2XTBI PCS, SGMII Bridge, and Deterministic Latency Signals 6.1.8. 10/100/1000 Multiport Ethernet MAC with 1000BASE-X/SGMII PCS Signals 6.1.9. 10/100/1000 Ethernet MAC with 1000BASE-X/SGMII TBI (LVDS I/O only) PCS Signals 6.1.10. 10/100/1000 Ethernet MAC with 1000BASE-X/SGMII PCS and Embedded PMA Signals 6.1.11. 10/100/1000 Multiport Ethernet MAC with 1000BASE-X/SGMII PCS and Embedded PMA Signals 6.1.12. 1000BASE-X/SGMII PCS Signals 6.1.13. 1000BASE-X/SGMII 2XTBI PCS Signals 6.1.14. 1000BASE-X/SGMII PCS and PMA Signals
126.96.36.199. Clock and Reset Signals 188.8.131.52. Clock Enabler Signals 184.108.40.206. MAC Control Interface Signals 220.127.116.11. MAC Status Signals 18.104.22.168. MAC Receive Interface Signals 22.214.171.124. MAC Transmit Interface Signals 126.96.36.199. Pause and Magic Packet Signals 188.8.131.52. MII/GMII/RGMII Signals 184.108.40.206. PHY Management Signals 220.127.116.11. ECC Status Signals
18.104.22.168. IEEE 1588v2 RX Timestamp Signals 22.214.171.124. IEEE 1588v2 TX Timestamp Signals 126.96.36.199. IEEE 1588v2 TX Timestamp Request Signals 188.8.131.52. IEEE 1588v2 TX Insert Control Timestamp Signals 184.108.40.206. IEEE 1588v2 Time-of-Day (TOD) Clock Interface Signals 220.127.116.11. IEEE 1588v2 PCS Phase Measurement Clock Signal 18.104.22.168. IEEE 1588v2 PHY Path Delay Interface Signals
7.1. Optimizing Clock Resources in Multiport MAC with PCS and Embedded PMA 7.2. Sharing PLLs in Devices with LVDS Soft-CDR I/O 7.3. Sharing PLLs in Devices with GIGE PHY 7.4. Sharing Transceiver Quads 7.5. Migrating From Old to New User Interface For Existing Designs 7.6. Clocking Scheme of MAC with 2XTBI PCS and Embedded PMA
10.6.1. alt_tse_mac_get_common_speed() 10.6.2. alt_tse_mac_set_common_speed() 10.6.3. alt_tse_phy_add_profile() 10.6.4. alt_tse_system_add_sys() 10.6.5. triple_speed_ethernet_init() 10.6.6. tse_mac_close() 10.6.7. tse_mac_raw_send() 10.6.8. tse_mac_setGMII mode() 10.6.9. tse_mac_setMIImode() 10.6.10. tse_mac_SwReset()
- 6.1.5. 10/100/1000 Ethernet MAC Without Internal FIFO Buffers with 1000BASE-X/SGMII 2XTBI PCS Signals
- 6.1.6. 10/100/1000 Ethernet MAC Without Internal FIFO Buffers with IEEE 1588v2 and 1000BASE-X/SGMII 2XTBI PCS Signals
6.1.7. 10/100/1000 Ethernet MAC Without Internal FIFO Buffers with IEEE 1588v2, 1000BASE-X/SGMII 2XTBI PCS, SGMII Bridge, and Deterministic Latency Signals
22.214.171.124. MAC Receive Interface Signals
|Name||Avalon Streaming Signal Type||I/O||Description|
|Avalon Streaming Signals|
(In Platform Designer: receive_clock_connection)
|clk||I||Receive clock. All signals on the Avalon streaming receive interface are synchronized on the rising edge of this clock. Set this clock to the frequency required to get the desired bandwidth on this interface. This clock can be completely independent from rx_clk.|
|ff_rx_dval||valid||O||Receive data valid. When asserted, this signal indicates that the data on the following signals are valid: ff_rx_data[(DATAWIDTH -1):0], ff_rx_sop, ff_rx_eop, rx_err[5:0], rx_frm_type[3:0], and rx_err_stat[17:0].|
|ff_rx_data [(DATAWIDTH-1):0]||data||O||Receive data. When DATAWIDTH is 32, the first byte received is ff_rx_data[31:24] followed by ff_rx_data[23:16] and so forth.|
|ff_rx_mod[1:0]||empty||O||Receive data modulo. Indicates invalid bytes in the final frame word:
This signal applies only when DATAWIDTH is set to 32.
|ff_rx_sop||startofpacket||O||Receive start of packet. Asserted when the first byte or word of a frame is driven on ff_rx_data[(DATAWIDTH-1):0].|
|ff_rx_eop||endofpacket||O||Receive end of packet. Asserted when the last byte or word of frame data is driven on ff_rx_data[(DATAWIDTH-1):0].|
|ff_rx_rdy||ready||I||Receive application ready. Assert this signal on the rising edge of ff_rx_clk when the user application is ready to receive data from the MAC function.|
|rx_err[5:0]||error||O||Receive error. Asserted with the final byte in the frame to indicate that an error was detected when receiving the frame. See rx_err Bit Description for the bit description.|
|ff_rx_dsav||—||O||Receive frame available. When asserted, this signal indicates that the internal receive FIFO buffer contains some data to be read but not necessarily a complete frame. The user application may want to start reading from the FIFO buffer.
This signal remains deasserted in the store and forward mode.
|rx_frm_type[3:0]||—||O||Frame type. See rx_frm_type Bit Description for the bit description.|
|ff_rx_a_full||—||O||Asserted when the FIFO buffer reaches the almost-full threshold.|
|ff_rx_a_empty||—||O||Asserted when the FIFO buffer goes below the almost-empty threshold.|
|rx_err_stat[17:0]||—||O|| rx_err_stat: One indicates that the receive frame is a stacked VLAN frame.
rx_err_stat: One indicates that the receive frame is either a VLAN or stacked VLAN frame.
rx_err_stat[15:0]: The value of the length/type field of the receive frame.
|3||Indicates VLAN frames. Asserted with ff_rx_sop and remains asserted until the end of the frame.|
|2||Indicates broadcast frames. Asserted with ff_rx_sop and remains asserted until the end of the frame.|
|1||Indicates multicast frames. Asserted with ff_rx_sop and remains asserted until the end of the frame.|
|0||Indicates unicast frames. Asserted with ff_rx_sop and remains asserted until the end of the frame.|
|5||Collision error. Asserted when the frame was received with a collision.|
|4||Corrupted receive frame caused by PHY or PCS error. Asserted when the error is detected on the MII/GMII/RGMII.|
|3||Truncated receive frame. Asserted when the receive frame is truncated due to an overflow in the receive FIFO buffer.|
|2 17||CRC error. Asserted when the frame is received with a CRC-32 error. This error bit applies only to frames with a valid length. Refer to Length Checking.|
|1 17||Invalid length error. Asserted when the receive frame has an invalid length as defined by the IEEE Standard 802.3. For more information on the frame length, refer to Length Checking.|
|0||Receive frame error. Indicates that an error has occurred. It is the logical OR of rx_err[5:1].|
17 Bits 1 and 2 are not mutually exclusive. Ignore CRC error rx_err signal if it is asserted at the same time as the invalid length error rx_err signal.
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