- 6.1.5. 10/100/1000 Ethernet MAC Without Internal FIFO Buffers with 1000BASE-X/SGMII 2XTBI PCS Signals
- 6.1.6. 10/100/1000 Ethernet MAC Without Internal FIFO Buffers with IEEE 1588v2 and 1000BASE-X/SGMII 2XTBI PCS Signals
7.4. Sharing Transceiver Quads
The dynamic reconfiguration is always turned on in devices other than Arria® GX and Stratix® II GX. When the dynamic reconfiguration is turned on in designs targeting devices other than Intel® Arria® 10, Stratix® V, Arria® V, Intel® Cyclone® 10 GX, and Cyclone® V, Intel recommends that you connect the dynamic reconfiguration signals to the ALTGX_RECONFIG megafunction.
In Stratix® V, Arria® V, and Cyclone® V devices, Intel recommends that you connect the dynamic reconfiguration signals to the Transceiver Reconfiguration Controller megafunction. For transceiver quad sharing between Triple-Speed Ethernet Intel® FPGA IP and other IPs that target these devices, reset signal for all the cores must be from the same source.
Refer to the respective device handbook for more information on dynamic reconfiguration signals in Intel FPGA devices.
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