Triple-Speed Ethernet Intel® FPGA IP User Guide

ID 683402
Date 12/19/2022
Document Table of Contents

6.2.3. GMII Transmit

On transmit, all data transfers are synchronous to the rising edge of tx_clk. The GMII data enable signal gm_tx_en is asserted to indicate the start of a new frame and remains asserted until the last byte of the frame is present on gm_tx_d[7:0] bus. Between frames, gm_tx_en remains deasserted.

If a frame is received on the Avalon® streaming interface with an error (asserted with ff_tx_eop), the frame is subsequently transmitted with the GMII gm_tx_err error signal at any time during the frame transfer.

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