Triple-Speed Ethernet Intel® FPGA IP User Guide

ID 683402
Date 7/22/2024
Public
Document Table of Contents

6.1.7.1. Deterministic Latency Clock Signals

Table 84.  Deterministic Latency Clock Signals
Name I/O Width Description
i_dl_sampling_clk I 1 Sampling clock for deterministic latency logic. The default frequency value is 228.571429 MHz.