Triple-Speed Ethernet Intel® FPGA IP User Guide

ID 683402
Date 10/12/2023
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Document Table of Contents
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6.1.7.1. Deterministic Latency Clock Signals

Table 84.  Deterministic Latency Clock Signals
Name I/O Width Description
i_dl_sampling_clk I 1 Sampling clock for deterministic latency logic. The default frequency value is 228.571429 MHz.