- 6.1.5. 10/100/1000 Ethernet MAC Without Internal FIFO Buffers with 1000BASE-X/SGMII 2XTBI PCS Signals
- 6.1.6. 10/100/1000 Ethernet MAC Without Internal FIFO Buffers with IEEE 1588v2 and 1000BASE-X/SGMII 2XTBI PCS Signals
7.1.1. MAC and PCS With GX Transceivers
- Utilize the same reset signal for all MAC instances if you do not require a separate reset for each instance.
- Utilize the same reference clock for all PMA quads
- Utilize the same clock source to drive the reference clock, FIFO transmit and receive clocks, and system clocks, if these clocks run at the same frequency.
The Intel® Quartus® Prime software automatically optimizes the TBI transmit clocks. Only one clock source drives the TBI transmit clocks from each PMA quad.
The calibration clock (gxb_cal_blk_clk) calibrates the termination resistors in all transceiver channels in a device. As there is only one calibration circuit in each device, one clock source suffices.
If you do not constrain the PLL inputs and outputs in your design, add derive_pll_clocks in the timing constraint file to ensure that the Timing Analyzer automatically creates derived clocks for the PLL outputs.
Note to Clock Distribution in MAC and SGMII PCS with GXB Configuration—Optimal Case:
- The PMA layer in devices with GX transceivers uses ALTGX IP.
In addition to the aforementioned optimization options, the TBI transmit and receive clocks can be used to drive the MAC transmit and receive clocks, respectively.
Note to Clock Distribution in MAC and 1000BASE-X PCS with GXB Configuration—Optimal Case :
- The PMA layer in devices with GX transceivers uses ALTGX megafunctions.
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