AN 802: Intel® Stratix® 10 SoC Device Design Guidelines

ID 683117
Date 12/14/2020
Document Table of Contents

2.4.2. USB Interface Design Guidelines4.1.2. USB Interface Design Guidelines

The Intel® Stratix® 10 HPS can connect its embedded USB MACs directly to industry-standard USB 2.0 ULPI PHYs using the 1.8 V dedicated HPS I/O. No FPGA routing resources are used and timing is fixed, which simplifies design.

This guide describes the design guidelines covering all supported speeds of PHY operation: High-Speed (HS) 480 Mbps, Full-Speed (FS) 12 Mbps, and Low-Speed (LS) 1.5 Mbps.

GUIDELINE: Intel® recommends that you design the board to support both USB PHY modes where the device supplies the clock versus where an external clock is the source.

The Stratix 10 SoC Development Kit uses the Microchip USB3320 USB PHY. This device is known to work with the HPS USB module.

The interface between the ULPI MAC and PHY on the Intel® Stratix® 10 SoC consists of 8-bit data and the following control signals:
  • STP
  • NXT
  • DIR

Lastly a static clock of 60MHz is driven from the PHY or from an external oscillator and is required for operation, including some register accesses from the HPS to the USB MAC. Ensure the PHY manufacturer recommendations for RESET and power-up are followed.

If your USB PHY supports both input and output clock modes, Intel® recommends that you design your board to support both modes to mitigate potential timing issues. Typically, these modes are selected through passive bootstrap pins that are either pulled high or low.
  • Output Mode—In output clock mode, the clock is generated by the USB PHY. All signals are synchronized to this clock.
    Figure 17. Output Mode
  • Input Mode—In input clock mode, the PHY receives a clock from an external source. All signals are synchronized to the clock. In this mode, the clock can be generated by a PLL in the FPGA or by an external source.
    Figure 18. Input Mode

GUIDELINE: Ensure that the USB signal trace lengths are minimized.

At 60 MHz, the period is 16.67 ns and in that time, for example, the clock must travel from the external PHY to the MAC and then the data and control signals must travel from the MAC to the PHY. Because there is a round-trip delay, the maximum length of the clock and ULPI signals are important. Based on preliminary timing data the maximum length is recommended to be less than 7 inches. This is based on a PHY with a 5 ns Tco spec. If the specification is slower the total length must be shortened accordingly.
Figure 19. Trace Length
If there is little setup timing margin on the USB PHY end of the bus, sometimes you can switch the PHY to input clock mode and supply a 60 MHz clock source from the board.
Figure 20. System Diagram and Board Spec

GUIDELINE: Ensure that signal integrity is considered.

Signal integrity is important mostly on the CLK signal driven from the PHY to the MAC in the HPS. Because these signals are point-to-point with a maximum length, they can usually run unterminated but Intel® recommends to simulate the traces to make sure the reflections are minimized. Using the 50-ohm output setting from the FPGA is typically recommended unless the simulations show otherwise. A similar setting should be used from the PHY vendor if possible.

GUIDELINE: Design properly for OTG operation, if used.

When On-the-Go (OTG) functionality is used, the SoC can become a host or endpoint. When in host mode consider the power delivery, such as when you are supporting a USB Flash drive, or potentially a USB Hard Drive. These power requirements and reverse currents must be accounted for typically using external diodes and current limiters such as those used on the Intel FPGA development kits for Stratix 10 SoC.

For more information about the " Intel® Stratix® 10 SoC Development Board Schematics", refer to the Stratix 10 FPGA Development Kit User Guide.

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