AN 802: Intel® Stratix® 10 SoC Device Design Guidelines

Download
ID 683117
Date 12/14/2020
Public
Document Table of Contents

2.3. Design Considerations for Connecting Device I/O to HPS Peripherals and Memory

One of the most important considerations when configuring the HPS is to understand how the I/O is organized in the Intel® Stratix® 10 SoC devices.

1. HPS Dedicated I/O

These 48 I/O are physically located inside the HPS, are dedicated for the HPS, and are used for the HPS clock and peripherals, including mass storage flash memory.

2. SDM Dedicated I/O

The SDM has 24 dedicated I/Os, which include JTAG, clock, reset, configuration, reference voltages, boot and configuration flash interfaces, and MSEL.

3. HPS EMIF I/O

There are three modular I/O banks that can connect to SDRAM memory. One of the I/O banks is used to connect the address, command and ECC data signals. The other two banks are for connecting the data signals.

4. FPGA I/O

You can use general purpose I/O for FPGA logic, FPGA external memory interfaces and high-speed serial interfaces. It is possible to export most HPS peripheral interfaces to the FPGA fabric for custom adaptation and routing to FPGA I/O.

The table below summarizes the characteristics of each I/O type.
Table 5.  Summary of SoC-FPGA I/O Types
  Dedicated HPS I/O Dedicated SDM I/O HPS EMIF I/O FPGA I/O
Number of Available I/O 48 24 3 I/O 48 banks All other device I/O
Location Inside the HPS

Inside the SDM

FPGA I/O Banks 2L, 2M, 2N I/O Columns are in the FPGA device
Voltages Supported 1.8V 1.8V LVDS I/O bank support for DDR3 and DDR4 protocols LVDS I/O bank, 3V I/O bank and high-speed serial transceivers
Purpose

HPS Clock, HPS peripherals, mass storage flash, HPS JTAG

FPGA JTAG through SDM dedicated pins, clock, reset, configuration, reference voltages, boot and configuration flash interfaces HPS main memory General purpose and transceiver I/O
Timing Constraints Fixed Fixed Provided by memory controller IP User defined
Recommended Peripherals

HPS peripheral I/O such as Ethernet PHY, USB PHY, mass storage flash (NAND, SD/MMC), TRACE debug.

Boot and configuration source, FPGA JTAG through SDM dedicated pins, and MSEL signals are connected to the SDM. DDR3, DDR4, and SDRAM

Slow speed HPS peripherals (I2C, SPI, EMAC-MII), FPGA I/O such as FPGA EMIFs, High Speed LVDS I/O, transceiver I/O, other parallel and control/status I/O.

For more information about console output during boot and configuration, refer to the "UART Interface Design Guidelines" section.

Did you find the information on this page useful?

Characters remaining:

Feedback Message