AN 802: Intel® Stratix® 10 SoC Device Design Guidelines

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ID 683117
Date 12/14/2020
Public
Document Table of Contents
Document Table of Contents
1. Introduction to the Intel® Stratix® 10 SoC Device Design Guidelines 2. Board Design Guidelines for Stratix 10 SoC FPGAs 3. Interfacing to the FPGA for Stratix 10 SoC FPGAs 4. System Considerations for Stratix 10 SoC FPGAs 5. Embedded Software Design Guidelines for Intel® Stratix® 10 SoC FPGAs 6. Recommended Resources for Stratix 10 SoC FPGAs
1. Introduction to the Intel® Stratix® 10 SoC Device Design Guidelines
1.1. Introduction to the Stratix 10 SoC Device Design Guidelines Revision History
2. Board Design Guidelines for Stratix 10 SoC FPGAs
2.1. Pin Connection Considerations for Board Design 2.2. HPS Clocking and Reset Design Considerations 2.3. Design Considerations for Connecting Device I/O to HPS Peripherals and Memory 2.4. Design Guidelines for HPS Interfaces 2.5. HPS EMIF Design Considerations 2.6. HPS Memory Debug 2.7. Boundary Scan for HPS 2.8. Embedded Software Debugging and Trace 2.9. Board Design Guidelines for Intel® Stratix® 10 SoC FPGAs Revision History
2.1. Pin Connection Considerations for Board Design
2.1.1. Board-Related Intel® Quartus® Prime Settings
2.1.1. Board-Related Intel® Quartus® Prime Settings
2.1.1.1. Unused Pins
2.2. HPS Clocking and Reset Design Considerations
2.2.1. HPS Clock Planning 2.2.2. Early Pin Planning and I/O Assignment Analysis 2.2.3. Pin Features and Connections for HPS Clocks, Reset and PoR 2.2.4. Direct to Factory Pin Support for Remote System Update (RSU) Feature 2.2.5. Internal Clocks 2.2.6. HPS Peripheral Reset Management
2.3. Design Considerations for Connecting Device I/O to HPS Peripherals and Memory
1. HPS Dedicated I/O=bij1501700196143__section_cpl_f3c_dx 2. SDM Dedicated I/O=bij1501700196143__section_dyv_f3c_dx 3. HPS EMIF I/O=bij1501700196143__section_q2z_f3c_dx 4. FPGA I/O=bij1501700196143__section_qkc_g3c_dx 2.3.1. HPS Pin Multiplexing Design Considerations 2.3.2. HPS I/O Settings: Constraints and Drive Strengths
2.4. Design Guidelines for HPS Interfaces
2.4.1. HPS EMAC PHY Interfaces 2.4.2. USB Interface Design Guidelines 2.4.3. SD/MMC and eMMC Card Interface Design Guidelines 2.4.4. Design Guidelines for Flash Interfaces 2.4.5. UART Interface Design Guidelines 2.4.6. I2C Interface Design Guidelines
2.4.1. HPS EMAC PHY Interfaces
2.4.1.1. PHY Interfaces 2.4.1.2. PHY Interfaces Connected Through FPGA I/O 2.4.1.3. MDIO 2.4.1.4. Common PHY Interface Design Considerations
2.4.1.1. PHY Interfaces
2.4.1.1.1. RMII 2.4.1.1.2. RGMII
2.4.1.2. PHY Interfaces Connected Through FPGA I/O
2.4.1.2.1. GMII/MII 2.4.1.2.2. Adapting to RGMII 2.4.1.2.3. Adapting to RMII 2.4.1.2.4. Adapting to SGMII
2.4.1.4. Common PHY Interface Design Considerations
2.4.1.4.1. Signal Integrity
2.4.4. Design Guidelines for Flash Interfaces
2.4.4.1. NAND Flash Interface Design Guidelines
2.5. HPS EMIF Design Considerations
2.5.1. Considerations for Connecting HPS to SDRAM 2.5.2. HPS SDRAM I/O Locations
3. Interfacing to the FPGA for Stratix 10 SoC FPGAs
3.1. Overview of HPS Memory-Mapped Interfaces 3.2. Recommended System Topologies 3.3. Recommended Starting Point for HPS-to-FPGA Interface Designs 3.4. Timing Closure for FPGA Accelerators 3.5. Information on How to Configure and Use the Bridges 3.6. Interfacing to the FPGA for Intel® Stratix® 10 SoC FPGAs Revision History
3.1. Overview of HPS Memory-Mapped Interfaces
3.1.1. HPS-to-FPGA Bridge 3.1.2. Lightweight HPS-to-FPGA Bridge 3.1.3. FPGA-to-HPS Bridge 3.1.4. FPGA-to-SDRAM Ports 3.1.5. Interface Bandwidths
3.2. Recommended System Topologies
3.2.1. HPS Accesses to FPGA Fabric 3.2.2. MPU Sharing Data with FPGA 3.2.3. Examples of Cacheable and Non-Cacheable Data Accesses From the FPGA
3.2.3. Examples of Cacheable and Non-Cacheable Data Accesses From the FPGA
3.2.3.1. Example 1: FPGA Reading Data from HPS SDRAM Directly 3.2.3.2. Example 2: FPGA Writing Data into HPS SDRAM Directly 3.2.3.3. Example 3: FPGA Reading Cache Coherent Data from HPS 3.2.3.4. Example 4: FPGA Writing Cache Coherent Data to HPS
4. System Considerations for Stratix 10 SoC FPGAs
4.1. Timing Considerations 4.2. Maximizing Performance 4.3. System Level Cache Coherency 4.4. System Considerations for Stratix 10 SoC FPGAs Revision History
4.1. Timing Considerations
4.1.1. Timing Closure for FPGA Accelerators 4.1.2. USB Interface Design Guidelines
4.1.1. Timing Closure for FPGA Accelerators
4.1.1.1. HPS First and FPGA First Boot Considerations
5. Embedded Software Design Guidelines for Intel® Stratix® 10 SoC FPGAs
5.1. Overview 5.2. Assembling the Components of Your Software Development Platform 5.3. Golden Hardware Reference Design (GHRD) 5.4. Selecting an Operating System for Your Application 5.5. Assembling Your Software Development Platform for Linux* 5.6. Assembling your Software Development Platform for a Bare-Metal Application 5.7. Assembling your Software Development Platform for Partner OS or RTOS 5.8. Choosing the Bootloader Software 5.9. Selecting Software Tools for Development, Debug and Trace 5.10. Boot And Configuration Considerations 5.11. System Reset Considerations 5.12. Flash Considerations 5.13. Embedded Software Debugging and Trace 5.14. Embedded Software Design Guidelines for Intel® Stratix® 10 SoC FPGAs Revision History
5.4. Selecting an Operating System for Your Application
5.4.1. Using Linux* or RTOS 5.4.2. Developing a Bare-Metal Application 5.4.3. Using the Bootloader as a Bare-Metal Framework 5.4.4. Using Symmetrical vs. Asymmetrical Multiprocessing (SMP vs. AMP) Modes
5.5. Assembling Your Software Development Platform for Linux*
5.5.1. Golden System Reference Design (GSRD) for Linux* 5.5.2. Source Code Management Considerations
5.9. Selecting Software Tools for Development, Debug and Trace
5.9.1. Selecting Software Build Tools 5.9.2. Selecting Software Debug Tools 5.9.3. Selecting Software Trace Tools
5.10. Boot And Configuration Considerations
5.10.1. Configuration Sources 5.10.2. Configuration Flash 5.10.3. Configuration Clock 5.10.4. Selecting HPS Boot Options 5.10.5. HPS Boot Sources 5.10.6. Remote System Update (RSU)
5.12. Flash Considerations
5.12.1. Flash Programming Method 5.12.2. Using a Single flash for Both FPGA Configuration and HPS Mass Storage
6. Recommended Resources for Stratix 10 SoC FPGAs
6.1. Device Documentation 6.2. Tools and Software Web Pages 6.3. Recommended Resources for Intel® Stratix® 10 SoC FPGAs Revision History
1. Introduction to the Intel® Stratix® 10 SoC Device Design Guidelines
2. Board Design Guidelines for Stratix 10 SoC FPGAs
3. Interfacing to the FPGA for Stratix 10 SoC FPGAs
4. System Considerations for Stratix 10 SoC FPGAs
5. Embedded Software Design Guidelines for Intel® Stratix® 10 SoC FPGAs
6. Recommended Resources for Stratix 10 SoC FPGAs

2.3. Design Considerations for Connecting Device I/O to HPS Peripherals and Memory

One of the most important considerations when configuring the HPS is to understand how the I/O is organized in the Intel® Stratix® 10 SoC devices.

1. HPS Dedicated I/O

These 48 I/O are physically located inside the HPS, are dedicated for the HPS, and are used for the HPS clock and peripherals, including mass storage flash memory.

2. SDM Dedicated I/O

The SDM has 24 dedicated I/Os, which include JTAG, clock, reset, configuration, reference voltages, boot and configuration flash interfaces, and MSEL.

3. HPS EMIF I/O

There are three modular I/O banks that can connect to SDRAM memory. One of the I/O banks is used to connect the address, command and ECC data signals. The other two banks are for connecting the data signals.

4. FPGA I/O

You can use general purpose I/O for FPGA logic, FPGA external memory interfaces and high-speed serial interfaces. It is possible to export most HPS peripheral interfaces to the FPGA fabric for custom adaptation and routing to FPGA I/O.

The table below summarizes the characteristics of each I/O type.
Table 5.  Summary of SoC-FPGA I/O Types
  Dedicated HPS I/O Dedicated SDM I/O HPS EMIF I/O FPGA I/O
Number of Available I/O 48 24 3 I/O 48 banks All other device I/O
Location Inside the HPS

Inside the SDM

 FPGA I/O Banks 2L, 2M, 2N I/O Columns are in the FPGA device
Voltages Supported 1.8V 1.8V LVDS I/O bank support for DDR3 and DDR4 protocols LVDS I/O bank, 3V I/O bank and high-speed serial transceivers
Purpose

HPS Clock, HPS peripherals, mass storage flash, HPS JTAG

FPGA JTAG through SDM dedicated pins, clock, reset, configuration, reference voltages, boot and configuration flash interfaces HPS main memory General purpose and transceiver I/O
Timing Constraints Fixed Fixed Provided by memory controller IP User defined
Recommended Peripherals

HPS peripheral I/O such as Ethernet PHY, USB PHY, mass storage flash (NAND, SD/MMC), TRACE debug.

Boot and configuration source, FPGA JTAG through SDM dedicated pins, and MSEL signals are connected to the SDM. DDR3, DDR4, and SDRAM

Slow speed HPS peripherals (I2C, SPI, EMAC-MII), FPGA I/O such as FPGA EMIFs, High Speed LVDS I/O, transceiver I/O, other parallel and control/status I/O.

For more information about console output during boot and configuration, refer to the "UART Interface Design Guidelines" section.

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