AN 802: Intel® Stratix® 10 SoC Device Design Guidelines

ID 683117
Date 12/14/2020
Document Table of Contents

3. Interfacing to the FPGA for Stratix 10 SoC FPGAs

The memory-mapped connectivity between the HPS and the FPGA fabric is a crucial tool to maximize the performance of your design. Use the guidelines in this chapter for recommended topologies to optimize your system’s performance.

Design guidelines for the remainder of the FPGA portion of your design are provided in the Stratix 10 Device Design Guidelines.

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