AN 802: Intel® Stratix® 10 SoC Device Design Guidelines

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ID 683117
Date 12/14/2020
Public
Document Table of Contents

3.1. Overview of HPS Memory-Mapped Interfaces

The HPS exposes three memory-mapped interfaces between the HPS and FPGA.
  • HPS-to-FPGA bridge: 32-, 64-, or 128-bit wide Advanced Microcontroller Bus Architecture ( AMBA* ) Advanced eXtensible Interface ( AXI* )-4
  • Lightweight HPS-to-FPGA bridge: 32-bit wide AXI-4
  • FPGA-to-HPS bridge: 128-bit wide ACE*-Lite
  • FPGA-to-SDRAM AXI-4 port: three interfaces, 32, 64, or 128 bits wide, allowing the FPGA to directly access the HPS-connected SDRAM
Figure 11. Stratix 10 HPS Connectivity

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