AN 802: Intel® Stratix® 10 SoC Device Design Guidelines

ID 683117
Date 12/14/2020
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2.5.1. Considerations for Connecting HPS to SDRAM

The hard memory controller for the Intel® Stratix® 10 HPS is in the FPGA I/O columns along with the other hardware memory controllers. The HPS can use only one hard memory controller, and it is located closest to the HPS block in I/O bank 2M, where the address/command and ECC signals reside. Use I/O Bank 2N for 16-bit and 32-bit interface DQ/DQS data group signals. I/O Bank 2L is used for 64-bit interface DQ/DQS data group signals.

Instantiating the Intel® Stratix® 10 HPS EMIF IP

Connecting external SDRAM to the Intel® Stratix® 10 HPS requires the use of an EMIF IP that is specific to the HPS. Follow the below guidelines for properly instantiating and configuring the correct EMIF IP for the HPS.

GUIDELINE: Instantiate the Intel® Stratix® 10 External Memory Interfaces for HPS IP in Platform Designer.

You must use a specific EMIF IP in Platform Designer to connect the HPS to external SDRAM memory.

The EMIF module is found in the IP catalog pane by selecting: Library > Processors and Peripherals > Hard Processor Components > External Memory Interfaces for HPS Intel® Stratix® 10 .

GUIDELINE: Connect the hps_emif conduit to the HPS component

To connect the HPS to the EMIF in Platform Designer, you must connect the hps_emif conduit in the instantiated emif_s10_hps_0 module to the hps_emif conduit in the stratix10_hps_0 module.

GUIDELINE: You must provide a free running and stable reference clock source to external memory interface before the start of device configuration.

For more information, refer to the Intel® Stratix® 10 External Memory Interfaces IP User Guide.

GUIDELINE: Make sure the HPS EMIF IP block is not reset while the HPS is accessing external SDRAM or resources in the L3 SDRAM Interconnect.

Asserting reset to the HPS EMIF IP block should coincide with the HPS reset assertion unless the application can save and recover context in co-ordination with HPS EMIF IP reset assertion. This can be achieved simply by connecting the HPS EMIF reset input to one or a combination of resets from the following sources: HPS reset outputs (for example: h2f_reset, h2f_cold_reset), other resets in the system that also source an HPS cold reset input (for example: nCONFIG and HPS_COLD_nRESET reset input pin).

If the HPS EMIF IP is reset without resetting the HPS as described above, the application must put the L3 SDRAM Interconnect in reset using the brgmodrst register, bit 6 (ddrsch) in the Reset Manager before HPS EMIF IP reset assertion and not release it until after the HPS EMIF IOPLL has locked. Failure to do so can result in locking up the processor on subsequent accesses to external SDRAM or resources in the L3 SDRAM Interconnect.

GUIDELINE: Ensure that the HPS memory controller Data Mask (DM) pins are enabled.

When you instantiate the memory controller in Platform Designer, you must select the checkbox to enable the data mask pins. If this control is not enabled, data corruption occurs any time a master accesses data in SDRAM that is smaller than the native word size of the memory.
Note: The checkbox to enable data masking is found in the "Parameters" tab for the External Memory Interfaces for HPS Intel® Stratix® 10 Intel® FPGA IP within the Topology section of the memory sub-tab.

GUIDELINE: Ensure that you choose only DDR3 or DDR4 components or modules in configurations that are supported by the Stratix 10 EMIF for HPS IP and your specific device and package combination.

Intel's External Memory Interface Spec Estimator is a parametric tool that allows you to compare supported external memory interface types, configurations and maximum performance characteristics in Intel FPGA and SoC devices.

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