AN 802: Intel® Stratix® 10 SoC Device Design Guidelines

ID 683117
Date 12/14/2020
Document Table of Contents

5.10.2. Configuration Flash

The following QSPI devices are validated for Intel® Stratix® 10 SoC configuration:

Table 16.  QSPI Devices
Vendor Part Number Capacity
Micron* MT25QU128 128 Mb
Micron* MT25QU256 256 Mb
Micron* MT25QU512 512 Mb
Micron* MT25QU01G 1 Gb
Micron* MT25QU02G 2 Gb
Macronix* MX25U128 128 Mb
Macronix* MX25U256 256 Mb
Macronix* MX25U512 512 Mb
Macronix* MX66U512 512 Mb
Macronix* MX66U1G 1 Gb
Macronix* MX66U2G 2 Gb

GUIDELINE: When configuring FPGA from flash, select a compatible QSPI device.

GUIDELINE: Select the QSPI device that fits your design. Using a larger device allows for increases in the design bitstream size.

GUIDELINE: Do not reset the quad SPI flash when used as the configuration device and data storage device with FPGA.

If you reset the quad SPI flash during the FPGA configuration and reconfiguration, or when the QSPI is in READ, WRITE, and ERASE operations, this causes undefined behavior for quad SPI flash and the FPGA. To recover from the unresponsive behavior, you must power cycle your device. To reset the quad SPI flash using the external host, you must first complete the FPGA configuration and reconfiguration, or a quad SPI operation, and only then toggle the reset. The quad SPI operation is complete when the exclusive access to the quad SPI flash is closed by issuing the QSPI_CLOSE command from the Mailbox Client Intel® FPGA IP or CLOSE command from the Serial Flash Mailbox Client Intel® FPGA IP.

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