AN 802: Intel® Stratix® 10 SoC Device Design Guidelines

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ID 683117
Date 12/14/2020
Public
Document Table of Contents

2.4.1. HPS EMAC PHY Interfaces

There are three EMACs based on the Synopsys* DesignWare* 3504‑0 Universal 10/100/1000 Ethernet MAC IP version. When configuring an HPS component for EMAC peripherals within Platform Designer, you must select from one of the following supported PHY interfaces, located in the HPS Dedicated I/O Bank2, for each EMAC instance:
  • Reduced Media Independent Interface (RMII)
  • Reduced Gigabit Media Independent Interface (RGMII)
Note: RGMII- Internal Delay (RGMII-ID) is a component of the RGMII version 2.0 specification that defines the capability of a transmitter to add delay on the forwarded data path clock to center that clock in the data. It adds delay on both: TX_CLK at the transmitter (MAC) and RX_CLK at the transmitter (PHY). Pin muxes in the HPS Dedicated I/O Bank feature the ability to add up to 2.4ns of delay in increments of 150ps, which is more than the required 1.5ns to center the clock in the transmit data at the PHY.

GUIDELINE: When selecting a PHY device, consider the desired Ethernet rate, available I/O and available transceivers, PHY devices that offer the skew control feature, and device driver availability.

The Intel® Stratix® 10 SoC Development Kit uses the Microchip KSZ9031 Ethernet PHY. This device is known to work with the Intel® Stratix® 10 HPS Ethernet PHY interface and software device drivers.

It is possible to adapt the MII/GMII PHY interfaces exposed to the FPGA fabric by the HPS component to other PHY interface standards such as RMII, SGMII, SMII and TBI using soft adaptation logic in the FPGA and features in the general-purpose FPGA I/O and transceiver FPGA I/O.

For more information, refer to the device drivers available for your operating system of choice or the Linux device driver provided with the Intel® Stratix® 10 SoC development kit.

The EMAC provides a variety of PHY interfaces and control options through the HPS and the FPGA I/Os.

For designs that are pin-limited on HPS I/O, the EMAC can be configured to expose either a GMII or MII PHY interface to the FPGA fabric, which can be routed directly to FPGA I/O pins. Exposing the PHY interface to the FPGA fabric also allows adapting the GMII/MII to other PHY interface types such as SGMII and RMII using soft logic with the appropriate general purpose or transceiver I/O resources.
Note: You can connect PHYs to the HPS EMACs through the FPGA fabric using the GMII and MII bus interfaces for Gigabit and 10/100 Mbps access respectively.

GUIDELINE: A GMII-to-SGMII adapter is available to automatically adapt to transceiver-based SGMII optical modules.

The EMAC also provides the I2C instead of the MDIO for their control interface. The HPS or FPGA can use three of the five general purpose I2C peripherals for controlling the PHY devices:
  • i2c_emac_0
  • i2c_emac_1
  • i2c_emac_2
2 The HPS Dedicated I/O Bank consists of 48 I/O with 1.8V signaling.

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