AN 802: Intel® Stratix® 10 SoC Device Design Guidelines

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ID 683117
Date 12/14/2020
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Document Table of Contents

2.9. Board Design Guidelines for Intel® Stratix® 10 SoC FPGAs Revision History

Table 10.  Board Design Guidelines for Stratix 10 SoC FPGAs Revision History

Document Version

Changes
2020.08.24 Added a new guideline, "Connection Guidelines for Unused HPS Block", to the Unused Pins section.
2019.04.17 Removed instances of RGMII in "HPS EMAC PHY Interfaces" and "Adapting to RGMII" sections because of timing issues utilizing RGMII.
2019.02.27 Added Remote System Update (RSU) content.
2018.12.24
  • Updated the "HPS SDRAM I/O Locations" section with restrictions on where the PLL reference clock and RZQ pin must be placed.
  • Added mandatory Intel® Stratix® 10 HPS EMIF pin placement rules.
  • Removed the following sections:
    • I/O Bank 2M, Lanes 0,1,2 (Addr/Cmd)
    • I/O Bank 2M, Lane 3 (ECC)
    • I/O Bank, 2N (Data)
    • I/O Bank, 2L (Data, 64/72-bit interfaces)
2018.09.24
  • Changed the pin name from HPS_COLD_RESET to HPS_COLD_nRESET.
  • Updated the steps for configuring the HPS_COLD_nRESET to be on any open SDM I/O pin.
  • Added the GUIDELINE: Do not connect HPS_COLD_nRESET to other resets on the board in the "Pin Features and Connections for HPS Clocks, Reset and PoR" section.
2018.05.07
  • Added a guideline for implementing an SGMII PHY interface using FPGA transceiver I/O for an S10 HPS EMAC instance, since the TSE MAC IP with 1000BASE-X PCS option no longer provides an option for transceiver I/O.
  • Added a guideline to reflect that the HPS EMIF reference clocks are stable prior to FPGA configuration.
  • Removed instances of LPDDR3
2018.03.01
  • Replaced "SDM JTAG" with "FPGA JTAG through SDM dedicated pins" in the Summary of SoC-FPGA I/O Types table in the "Design Considerations for Connecting Device I/O to HPS Peripherals and Memory" section.
  • Corrected definition for HPS_COLD_nRESET, because it is not configured for "open drain".
  • Updated the "Boundary Scan for HPS" section with details about how to issue a boundary scan from the FPGA JTAG; and how to chain the JTAG.
2017.11.06 Initial release

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