AN 802: Intel® Stratix® 10 SoC Device Design Guidelines

ID 683117
Date 12/14/2020
Document Table of Contents

5.10.1. Configuration Sources

The initial FPGA configuration and the HPS FSBL are part of the initial configuration bitstream, which can be obtained from several sources:

  • Avalon® -ST Data Source: An external Avalon® -ST master provides the bitstream.
  • JTAG Interface: An external JTAG master (usually driven by a host tool) provides the bitstream.
  • SDM Flash: A flash device connected on SDM side provides the bitstream.

The following flash device types can be connected to SDM:

Table 15.   Flash Type Support Status
Flash Type Support Status


Currently supported in the Intel® Quartus® Prime Pro Edition 18.1 release


Will be supported in future Intel® Quartus® Prime Pro Edition releases

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