3.1.3. FPGA-to-HPS Bridge
GUIDELINE: Use the FPGA-to-HPS bridge for cache coherent memory accesses to the HPS from masters in the FPGA.
The FPGA-to-HPS bridge allows masters implemented in the FPGA fabric to access memory and peripherals inside the HPS. This bridge supports a fixed 128-bit data path. Platform Designer can handle the data width adaptation in the generated interconnect for narrow masters.
GUIDELINE: The FPGA-to-HPS bridge supports cache coherent memory accesses with the ACE-Lite protocol.
FPGA masters must use the ACE-Lite cache signaling extensions for cache coherent accesses.
For more information about the ACE-Lite protocol extensions for cache coherent transactions, refer to the AMBA* AXI and ACE Protocol Specification on the Arm* Developer website.
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